Complementary metal oxide semiconductor device
View Patent ↗The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.
1. A complementary metal oxide semiconductor (CMOS) device, comprising:
a PMOS with a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer; and
an NMOS with an N type metal gate, which comprises the NWFT layer, the NWFM layer and the metal layer, wherein the P type metal gate and the N type metal gate further comprise a top barrier layer disposed between the NWFM layer and the metal layer, and the NWFM layer is disposed between the NWFT layer and the top barrier layer and has a different material from materials of the NWFT layer and the top barrier layer.
2. The CMOS device according to claim 1 , wherein the P type metal gate sequentially comprises the bottom barrier layer, the PWFM layer, the NWFT layer, the NWFM layer and the metal layer.
3. The CMOS device according to claim 1 , wherein the N type metal gate sequentially comprises the NWFT layer, the NWFM layer and the metal layer.
4. The CMOS device according to claim 1 , wherein the N type metal gate does not comprises the bottom barrier layer and the PWFM layer.
5. The CMOS device according to claim 1 , wherein the NWFT layer comprises TiN or TaN.
6. The CMOS device according to claim 5 , wherein a concentration of nitrogen is greater than a concentration of titanium in the NWFT layer.
7. The CMOS device according to claim 5 , wherein a concentration of nitrogen is less than a concentration of titanium in the NWFT layer.
8. The CMOS device according to claim 1 , wherein the bottom barrier layer comprises a first bottom barrier layer and the second bottom barrier layer.
9. The CMOS device according to claim 8 , wherein the first bottom barrier layer comprises TiN and the second bottom barrier layer comprises TaN.
10. The CMOS device according to claim 1 , wherein the N type metal gate comprises an etch stop layer, and the NWFT layer is disposed between the etch stop layer and the NWFM layer, and the etch stop layer has an etching selectivity with respect to the NWFT layer.