Semiconductor device and method for fabricating the same
View Patent ↗A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal gate thereon and an interlayer dielectric (ILD) layer around the metal gate; removing part of the metal gate to form a recess; and depositing a mask layer in the recess and on the ILD layer while forming a void in the recess.
1. A method for fabricating semiconductor device, comprising:
providing a substrate having a metal gate thereon and a first interlayer dielectric (ILD) layer around the metal gate;
removing part of the metal gate to form a recess; and
depositing a mask layer in the recess and on the first ILD layer while forming a void in the recess.
2. The method of claim 1 , wherein the mask layer comprises silicon nitride or silicon carbon nitride.
3. The method of claim 1 , further comprising forming a first contact plug in the mask layer and the first ILD layer.
4. The method of claim 3 , wherein the top surfaces of the mask layer and the first contact plug are coplanar.
5. The method of claim 3 , further comprising:
forming a second ILD layer on the mask layer and the first contact plug;
forming a second contact plug in the second ILD layer and contacting the first contact plug; and
forming a third contact plug in the mask layer and the second ILD layer and contacting the metal gate.
6. The method of claim 5 , wherein the top surfaces of the second contact plug, the third contact plug, and the second ILD layer are coplanar.
7. The method of claim 1 , further comprising:
forming a second ILD layer on the mask layer;
forming a first contact plug in the mask layer, the first ILD layer, and the second ILD layer; and
forming a second contact plug in the mask layer and the second ILD layer and contacting the metal gate.
8. The method of claim 7 , wherein the top surfaces of the first contact plug, the second contact plug, and the second ILD layer are coplanar.
9. The method of claim 3 , further comprising:
forming a second contact plug in the mask layer and contacting the metal gate;
forming a second ILD layer on the mask layer, the first contact plug, and the second contact plug;
forming a third contact plug in the second ILD layer and contacting the first contact plug; and
forming a fourth contact plug in the second ILD layer and contacting the second contact plug.
10. The method of claim 9 , wherein the top surfaces of the first contact plug, the second contact plug, and the mask layer are coplanar.
11. The method of claim 9 , wherein the top surfaces of the third contact plug, the fourth contact plug, and the second ILD layer are coplanar.
12. A semiconductor device, comprising:
a substrate;
a metal gate on the substrate;
a first interlayer dielectric (ILD) layer around the metal gate;
a mask layer on the metal gate and the first ILD layer; and
a void in the mask layer and above the metal gate.
13. The semiconductor device of claim 12 , wherein the mask layer comprises silicon nitride or silicon carbon nitride.
14. The semiconductor device of claim 12 , wherein the void is lower than the top surface of the first ILD layer.
15. The semiconductor device of claim 12 , further comprising a first contact plug in the mask layer and the first ILD layer.
16. The semiconductor device of claim 15 , wherein the top surfaces of the mask layer and the first contact plug are coplanar.
17. The semiconductor device of claim 15 , further comprising:
a second ILD layer on the mask layer and the first contact plug;
a second contact plug in the second ILD layer and contacting the first contact plug; and
a third contact plug in the mask layer and the second ILD layer and contacting the metal gate.
18. The semiconductor device of claim 17 , wherein the top surfaces of the second contact plug, the third contact plug, and the second ILD layer are coplanar.
19. The semiconductor device of claim 12 , further comprising:
a second ILD layer on the mask layer;
a first contact plug in the mask layer, the first ILD layer, and the second ILD layer; and
a second contact plug in the mask layer and the second ILD layer and contacting the metal gate.
20. The semiconductor device of claim 19 , wherein the top surfaces of the first contact plug, the second contact plug, and the second ILD layer are coplanar.
21. The semiconductor device of claim 15 , further comprising:
a second contact plug in the mask layer and contacting the metal gate;
a second ILD layer on the mask layer, the first contact plug, and the second contact plug;
a third contact plug in the second ILD layer and contacting the first contact plug; and
a fourth contact plug in the second ILD layer and contacting the second contact plug.
22. The semiconductor device of claim 21 , wherein the top surfaces of the first contact plug, the second contact plug, and the mask layer are coplanar.
23. The semiconductor device of claim 21 , wherein the top surfaces of the third contact plug, the fourth contact plug, and the second ILD layer are coplanar.
24. The semiconductor device of claim 12 , wherein the top surface of the mask layer is higher than the top surface of the metal gate.