Group III-V transistor with semiconductor field plate
There are disclosed herein various implementations of a group III-V transistor with a semiconductor field plate. Such a group III-V transistor includes a group III-V heterostructure situated over a substrate and configured to produce a two-dimensional electron gas (2DEG). In addition, the group III-V transistor includes a source electrode, a drain electrode, and a gate situated over the group heterostructure. The group III-V transistor also includes an insulator layer over the group III-V heterostructure and situated between the gate and the drain electrode, and a semiconductor field plate situated between the gate and the drain electrode, over the insulator layer.
1. A group III-V transistor comprising:
a group III-V heterostructure situated over a substrate and configured to produce a two-dimensional electron gas (2DEG);
a source electrode, a drain electrode, and a gate situated over said group III-V heterostructure;
an insulator layer over said group III-V heterostructure and situated between said gate and said drain electrode,
wherein a gate-facing end of said insulator layer is in contact with, and terminates at, a side surface of said gate,
wherein a drain electrode-facing end of said insulator layer is in contact with a side surface, and a portion of an upper surface, of said drain electrode;
a semiconductor field plate situated between said gate and said drain electrode, over said insulator layer,
wherein a gate-facing end of said semiconductor field plate is in contact with said side surface, and a portion of an upper surface, of said gate,
wherein a drain electrode-facing end of said semiconductor field plate is in contact with a portion of the upper surface of said drain electrode;
wherein said semiconductor field plate adjoins said drain electrode.
2. The group III-V transistor of claim 1 , wherein said semiconductor field plate has a sheet resistance in a range from approximately 10 4 ohms/square to approximately 10 7 ohms/square.
3. The group III-V transistor of claim 1 , wherein said semiconductor field plate comprises an amorphous semiconductor layer.
4. The group III-V transistor of claim 1 , wherein said semiconductor field plate comprises a single crystalline semiconductor layer.
5. The group III-V transistor of claim 1 , wherein said semiconductor field plate comprises a polycrystalline semiconductor layer.
6. The group III-V transistor of claim 1 , wherein said semiconductor field plate comprises a polycrystalline III-Nitride layer.
7. The group III-V transistor of claim 1 , wherein said semiconductor field plate comprises an amorphous III-Nitride layer.
8. A III-Nitride transistor comprising:
a gallium nitride (GaN) channel layer situated over a substrate;
an aluminum gallium nitride (AlGaN) barrier layer situated over said GaN channel layer, said AlGaN barrier layer and said GaN channel layer configured to produce a two-dimensional electron gas (2DEG);
a source electrode, a drain electrode, and a gate situated over said AlGaN barrier layer;
an insulator layer over said AlGaN barrier layer and situated between said gate and said drain electrode,
wherein a gate-facing end of said insulator layer is in contact with, and terminates at, a side surface of said gate,
wherein a drain electrode-facing end of said insulator layer is in contact with a side surface, and a portion of an upper surface, of said drain electrode;
a semiconductor field plate situated between said gate and said drain electrode, over said insulator layer,
wherein a gate-facing end of said semiconductor field plate is in contact with said side surface, and a portion of an upper surface, of said gate,
wherein a drain electrode-facing end of said semiconductor field plate is in contact with a portion of the upper surface of said drain electrode;
wherein said semiconductor field plate adjoins said drain electrode.
9. The III-Nitride transistor of claim 8 , wherein said semiconductor field plate has a sheet resistance in a range from approximately 10 4 ohms/square to approximately 10 7 ohms/square.
10. The Ill-Nitride transistor of claim 8 , wherein said semiconductor field plate comprises an amorphous semiconductor layer.
11. The III-Nitride transistor of claim 8 , wherein said semiconductor field plate comprises a single crystalline III-Nitride layer.
12. The III-Nitride transistor of claim 8 , wherein said semiconductor field plate comprises a polycrystalline III-Nitride layer.