Metadata storage associated with wear-level operation requests
View Patent ↗A method includes responding to a wear-level operation request by copying data from a first portion of a first memory array to a second portion of the first memory array, and copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array. The first memory array includes a NAND or NAND-based memory array, and the second memory array includes non-volatile memory including at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.
1. A method comprising:
copying information from a first portion of a first memory array to a second portion of the first memory array, wherein the first memory array comprises a NAND or NAND-based memory array; and
copying metadata associated with the information from a third portion of a second memory array to a fourth portion of the second memory array, wherein the second memory array comprises non-volatile memory.
2. The method of claim 1 , wherein said copying information and copying metadata are performed in parallel with one another.
3. The method of claim 1 , wherein said method further comprises modifying an address from identifying the first portion of the first memory array to identifying the second portion of the first memory array.
4. The method of claim 1 , further comprising setting a flag to indicate that the first portion of the first memory array is invalid, to indicate that the first portion of the first memory array no longer stores valid data, or both.
5. The method of claim 1 , wherein the second memory array comprises at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.
6. A memory device comprising:
a NAND or NAND-based memory array;
a nonvolatile memory; and
a flash translation layer configured to copy information from a first portion of the NAND or NAND-based memory array to a second portion of the NAND or NAND-based memory array and to copy metadata associated with the information from a third portion of the nonvolatile memory to a fourth portion of the nonvolatile memory.
7. The memory device of claim 6 , wherein the flash translation layer is configured to copy the information and to copy the metadata in parallel with one another.
8. The memory device of claim 6 , wherein the flash translation layer comprises a NAND driver and a PCM driver.
9. The memory device of claim 6 , wherein the metadata comprises sector numbers, virtual block addresses, or both, of the NAND or NAND-based memory array.
10. The memory device of claim 6 , wherein the flash translation layer comprises a wear-leveling module configured to monitor and evenly distribute a number of erase cycles per block of memory of the NAND or NAND-based memory array.
11. The memory device of claim 6 , wherein the flash translation layer is further configured to set a flag to indicate that the first portion of the NAND or NAND-based memory array is invalid, to indicate that the first portion of the NAND or NAND-based memory array no longer stores valid data, or both.
12. The memory device of claim 6 , wherein the nonvolatile memory comprises at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.
13. A system comprising:
a computer processor; and
a memory device operationally coupled to the computer processor, the memory device comprising:
a NAND or NAND-based memory array;
a nonvolatile memory; and
a flash translation layer configured to copy information from a first portion of the NAND or NAND-based memory array to a second portion of the NAND or NAND-based memory array and to copy metadata associated with the information from a third portion of the nonvolatile memory to a fourth portion of the nonvolatile memory.
14. The system of claim 13 , wherein the flash translation layer is configured to copy the information and to copy the metadata in parallel with one another.
15. The system of claim 13 , wherein the flash translation layer is further configured to modify an address from identifying the first portion of the NAND or NAND-based memory array to identifying the second portion of the NAND or NAND-based memory array.
16. The system of claim 13 , wherein the first portion is a first memory block of the NAND or NAND-based memory array and the second portion is a second memory block of the NAND or NAND-based memory array.
17. The system of claim 13 , wherein the flash translation layer comprises a NAND driver and a PCM driver.
18. The system of claim 13 , wherein the flash translation layer comprises a wear-leveling module configured to monitor and evenly distribute a number of erase cycles per block of memory of the NAND or NAND-based memory array.
19. The system of claim 13 , wherein the flash translation layer is further configured to set a flag to indicate that the first portion of the NAND or NAND-based memory array is invalid, to indicate that the first portion of the NAND or NAND-based memory array no longer stores valid data, or both.
20. The system of claim 13 , wherein the second memory array comprises at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.