High performance interconnect physical layer
A reset of a synchronization counter is synchronized to an external deterministic signal. Entry into the link transmitting state is further synchronized with the deterministic signal. A target latency is identified for a serial data link. A data sequence is received synchronized with a synchronization counter associated with the data link. Target latency can be maintained using the data sequence.
1. An apparatus comprising
interface logic implemented at least in part in hardware to:
differentially signal on a plurality of lanes,
transmit a plurality of flits, wherein the plurality of flits comprise a plurality of nibbles,
wherein a first one of the plurality of flits is to be transmitted with
a clean flit boundary such that each of the plurality of lanes is used to transmit starting nibbles of the first flit in a first unit interval (UI) and starting nibbles of a second one of the plurality of flits are to be transmitted with final nibbles of the first flit
on the plurality of lanes during a subsequent UI.
2. The apparatus of claim 1 , wherein the plurality of flits comprises at least five flits to be transmitted over 48 UI before another one of the plurality of flits is to be transmitted with a clean flit boundary.
3. The apparatus of claim 1 , a flit comprises 192 bits and a nibble comprises 4 bits.
4. The apparatus of claim 3 , wherein bits of each flit are to be transmitted in an order starting with bit 4 n+ 3.
5. The apparatus of claim 1 , wherein the plurality of lanes comprises one of 8 lanes or 20 lanes.
6. The apparatus of claim 1 , wherein the interface logic comprises physical layer logic, link layer logic and protocol layer logic.
7. The apparatus of claim 6 , wherein the protocol layer logic is to support cache coherent transactions.
8. The apparatus of claim 1 , wherein the interface logic is included in a processor coupled in one socket of a server with at least two sockets.
9. The apparatus of claim 1 , wherein interface logic is included in a system on a chip (SoC).
10. The apparatus of claim 9 , wherein the SoC is coupled to a plurality of other SoCs in a micro-server.
11. The apparatus of claim 9 , further comprising a radio.
12. An apparatus comprising
a controller to interface between at least a first processor to recognize a first instruction set and second processor to recognize a second instruction set that is different from the first instruction set, the controller comprising interface logic implemented at least in part in hardware, wherein the interface logic is to:
couple to a serial, differential interconnect comprising a plurality of lanes;
transmit a plurality of flits, wherein each of the plurality of flits comprises a respective plurality of nibbles,
wherein a first one of the plurality of flits is to be transmitted with a clean flit boundary with starting nibbles of the first flit sent on each lane of the plurality of lanes in a first unit interval (UI), and starting nibbles of a second one of the plurality of flits are to be sent with final nibbles of the first flit on the plurality of lanes during a subsequent UI.
13. The apparatus of claim 12 , wherein each of the plurality of flits comprises 192 bits and 48 nibbles.
14. The apparatus of claim 13 , wherein the plurality of lanes comprises 20 lanes.
15. The apparatus of claim 12 , wherein the first and the second processor are coupled to the controller.
16. An apparatus comprising:
interface logic to differentially signal on a plurality of lanes,
the interface logic to logically group data into a plurality of quantums of information, wherein the interface logic is to transmit
at least a first portion of a first quantum of information of the plurality of quantums of information on all of the plurality of lanes during a first unit interval (UI); and
at least another portion of the first quantum of information together with a portion of a second quantum of information of the plurality of quantums of information on the plurality of lanes during a subsequent UI.
17. The apparatus of claim 16 , wherein the first portion of the first quantum of information is to be transmitted during at least the first four unit intervals (UIs), and wherein the other portion of the first quantum of information and the portion of the second quantum of information are to be transmitted together on the plurality of lanes during a subsequent four consecutive UIs.
18. The apparatus of claim 16 , wherein the first quantum of information includes 192 bits.
19. The apparatus of claim 16 , wherein the interface logic comprises protocol logic to support cache coherent transactions.