Semiconductor-on-insulator with back side strain topology

1. A semiconductor-on-insulator (SOI) structure comprising:

a patterned layer formed in an insulating material of the SOI structure, the patterned layer consisting of an excavated region and a pattern region;

a strain layer located beneath the patterned layer and in the excavated region and on the pattern region;

an active layer located above the strain layer and the patterned layer;

a field effect transistor formed in the active layer, wherein the field effect transistor comprises a source, a drain, and a channel; and

a handle layer located above the active layer;

wherein the channel lies completely within a lateral extent of the pattern region;

wherein the source and the drain each lie only partially within the lateral extent of the pattern region; and

wherein the strain layer alters a carrier mobility of the channel.

2. The semiconductor-on-insulator structure of claim 1 , wherein:

the patterned layer has a height equal to a depth of the excavated region;

the strain layer has a front surface in contact with the patterned layer and a back surface;

the strain layer has a thickness equal to a distance between the back surface and the front surface; and

a ratio of the height of the patterned layer to the thickness of the strain layer is within a range from 0.75 to 1.5.

3. The semiconductor-on-insulator structure of claim 2 , further comprising:

a buried insulator of the semiconductor-on-insulator structure that is in contact with both the patterned layer and the active layer;

wherein the buried insulator is less than 1 micron thick; and

wherein the patterned layer is formed on the buried insulator.

4. The semiconductor-on-insulator structure of claim 1 , further comprising:

a portion of the excavated region that extends laterally from below the source to beyond a periphery of the field effect transistor;

wherein a lateral dimension of the portion of the excavated region in a direction away from the channel is larger than a length of the channel by a factor of 10.

5. The semiconductor-on-insulator structure of claim 4 , wherein:

the channel of the field effect transistor is less than 1 micron long; and

the lateral dimension of the portion of the excavated region is greater than 10 microns.

6. The semiconductor-on-insulator structure of claim 1 , further comprising:

a buried insulator of the semiconductor-on-insulator structure;

wherein the buried insulator is the patterned layer.

7. The semiconductor-on-insulator structure of claim 6 , further comprising:

a counter-strain layer formed on a back side of the strain layer;

wherein the counter-strain layer exerts an opposite strain force on the active layer as compared to the strain layer.

8. A semiconductor structure comprising:

an active layer bonded to a handle layer, wherein the handle layer is on a first side of the active layer;

a patterned layer of insulating material on a second side of the active layer, wherein the pattern layer consists of an excavated region and a pattern region; and

a strain layer located on the pattern region and in the excavated region, wherein the strain layer exhibits a strain on a device in the active layer;

wherein the device is a field effect transistor having a source, a drain, and a channel, the channel being between the source and the drain; and

wherein the pattern region laterally at least fully encompasses the channel.

9. The semiconductor structure of claim 8 , wherein:

the patterned layer has a height equal to a depth of the excavated region;

the strain layer has a front surface in contact with the patterned layer and a back surface;

the strain layer has a thickness equal to a distance between the back surface and the front surface; and

a ratio of the height of the patterned layer to the thickness of the strain layer is within a range from 0.75 to 1.5.

10. The semiconductor structure of claim 9 , wherein:

the ratio is 1.

11. The semiconductor structure of claim 8 , further comprising:

a portion of the excavated region that extends laterally from a portion of the pattern region that partially encompasses the source to beyond a periphery of the device;

wherein a lateral dimension of the portion of the excavated region in a direction normal to a width of the channel and away from the channel is larger than a length of the channel by a factor of 10.

12. The semiconductor structure of claim 11 , wherein:

the channel of the device is less than 1 micron long; and

the lateral dimension of the portion of the excavated region is greater than 10 microns.

13. The semiconductor structure of claim 8 , further comprising:

a buried insulator on which the active layer is formed;

wherein the buried insulator is the patterned layer.

14. The semiconductor structure of claim 8 , wherein:

a portion of the source that lies within a lateral extent of pattern region has a first lateral dimension in a direction away from the channel;

the first lateral dimension is larger than a length of the channel.

15. A semiconductor structure comprising:

an etched patterned layer formed in an insulating layer on a back side of semiconductor structure;

a strain layer formed on the etched patterned layer;

a handle layer bonded to a front side of the semiconductor structure;

an active layer located between the patterned layer and the handle layer; and

a field effect transistor formed in the active layer, wherein the field effect transistor comprises an active area;

wherein the field effect transistor comprises a channel;

wherein a portion of the etched patterned layer has a lateral extent at least that of the channel;

wherein the field effect transistor has a lateral extent beyond the portion; and

wherein the strain layer is in contact with the active area.

16. The semiconductor structure of claim 15 , wherein:

the etched patterned layer has an etch depth;

the strain layer has a strain layer width; and

a ratio of the etch depth to the strain layer width is within a range from 0.75 to 1.5.

17. The semiconductor structure of claim 15 , further comprising:

a contiguous etched region of the etched pattern layer extends away from the portion to beyond a periphery of the field effect transistor;

wherein a dimension of the contiguous etched region measured along a direction parallel with the channel length is larger than the channel length by a factor of 10.

18. The semiconductor structure of claim 17 , further comprising:

the channel length is less than 1 micron; and

the dimension of the contiguous etched region is greater than 10 microns.

19. The semiconductor structure of claim 15 , further comprising:

a part of the active area that is outside a lateral scope of the channel but within a lateral scope of the portion has a first lateral dimension in a direction away from the channel and perpendicular to the channel width; and

the first lateral dimension is larger than the length of the channel.

20. The semiconductor structure of claim 15 , further comprising:

a buried insulator layer in contact with the active layer and the strain layer;

wherein the buried insulator layer is the patterned layer;

wherein the buried insulator layer is silicon dioxide; and

wherein the strain layer is silicon nitride.