IP Library Granted Patent US 9,858,101
Granted Patent B2
US 9,858,101 · App. 14/540,497 · Granted Jan 2, 2018

Virtual machine input/output thread management

Inventors: Michael Tsirkin (Raanana, IL); Paolo Bonzini (Milan, IT)
Assignee: RED HAT ISRAEL, LTD.
G06F9/45558G06F2009/45575G06F2009/45579
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Quick Facts
Patent No.
US 9,858,101
App. No.
14/540,497
Granted
Jan 2, 2018
Kind
B2
Abstract

A method performed by a physical computing system includes detecting an interrupt signal sent to a virtual processor being managed by the hypervisor, creating a map between the virtual processor and an Input/Output (I/O) thread associated with the interrupt signal, determining that the virtual processor is idle, finding the I/O thread associated with the idle virtual processor based on the map, and moving the I/O thread associated with the idle virtual processor up in a processing queue, the processing queue being for processes to be executed on a physical processor.

Claims (42)

1. A method performed by a physical computing system, the method comprising:

with a hypervisor, detecting an interrupt signal sent to a virtual processor being managed by the hypervisor;

creating a map between the virtual processor and an Input/Output (I/O) thread associated with the interrupt signal; and

in response to determining that the virtual processor is idle;

finding the I/O thread associated with the idle virtual processor based on the map; and

moving the I/O thread associated with the idle virtual processor up in a processing queue, the processing queue being for processes to be executed on a physical processor.

2. The method of claim 1 , wherein the map comprises a data structure that matches I/O threads with corresponding virtual processors.

3. The method of claim 1 , wherein an association within the map is made between the virtual processor and the I/O thread if the I/O thread sends a threshold number of interrupt signals to the virtual processor.

4. The method of claim 1 , further comprising, storing the map in hypervisor memory.

5. The method of claim 1 , wherein the map associates the I/O thread with the virtual processor and a virtual machine corresponding to the virtual processor.

6. The method of claim 1 , wherein the virtual processor is idle because the virtual processor executed a halt command.

7. The method of claim 1 , wherein the moving the I/O thread associated with the idle virtual processor up in a processing queue comprises lending execution time from the virtual processor to the I/O thread.

8. The method of claim 1 , wherein the map includes associations of multiple I/O threads to multiple additional virtual processors.

9. The method of claim 1 , wherein the map uses a thread identifier of the I/O thread to map the I/O thread to the virtual processor.

10. A computing system comprising:

a processor; and

a memory comprising computer readable instructions that when executed by the processor, cause the system to:

run a hypervisor to host a virtual machine that includes a number of virtual processors;

run a scheduler to manage a processing queue for execution of threads on the processor;

detect an interrupt signal sent to one of the virtual processors;

create a map between an Input/Output (I/O) thread associated with the interrupt signal and the one of the virtual processors; and

determine that the virtual processor is in an idle state, and in response;

use the map to find the I/O thread associated with the virtual processor in the idle state; and

cause the scheduler to move the I/O thread up in the processing queue.

11. The system of claim 10 , wherein to create the map, the processor is further to cause the system to create an entry in a data structure, the entry associating the I/O thread with the one of the virtual processors.

12. The system of claim 11 , wherein the entry in the data structure includes a thread identifier for the I/O thread.

13. The system of claim 11 , wherein the entry is created in response to detecting a threshold number of interrupt signals from the I/O thread to the one of the virtual processors.

14. The system of claim 10 , wherein the processor is further to cause the system to store the map in a hypervisor memory.

15. The system of claim 10 , wherein the map associates the I/O thread with the virtual processor and a virtual machine corresponding to the virtual processor.

16. The system of claim 10 , wherein to cause the scheduler to move the I/O thread up in the processing queue, the processor is further to cause the system to lend execution time allocated to the one of the virtual processors to the I/O thread.

17. The system of claim 10 , wherein the processor is further to cause the system to:

detect interrupt signals from other I/O threads sent to other virtual processors of the number of virtual processors being executed on the computing system; and

map the other I/O threads to the other virtual processors.

18. A method performed by a physical computing system, the method comprising:

with a hypervisor, monitoring interrupt signals sent to virtual processors;

creating a map between Input/Output (I/O) threads associated with the interrupt signals and the virtual processors;

with a scheduler, managing a processing queue for a set of threads to be executed on a host processor, the set of threads including the I/O threads; and

in response to determining that a first virtual processor of the virtual processors is in an idle state;

using the map to find the I/O thread associated with the first virtual processor; and

causing the scheduler to use execution time allocated to the first virtual processor for execution of the I/O thread associated with the first virtual processor.

19. The method of claim 18 , wherein the first virtual processor is idle because the virtual processor executed a halt command.

20. The method of claim 18 , wherein creating the map comprises, for each detected interrupt signal, create an entry in a data structure that links the I/O thread that sent that interrupt signal to the virtual processor to which that interrupt signal is being sent.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 13, 2014
From: TSIRKIN, MICHAEL; BONZINI, PAOLO
To: RED HAT ISRAEL, LTD.
Reel/Frame 034165/0562 →
Continuity (1)
Related Publication 20160139942A1 · May 19, 2016