IP Library Granted Patent US 9,214,527
Granted Patent B2
US 9,214,527 · App. 14/543,349 · Granted Dec 15, 2015

Methods of forming diodes

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Quick Facts
Patent No.
US 9,214,527
App. No.
14/543,349
Granted
Dec 15, 2015
Kind
B2
Abstract

Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

Claims (12)

1. A method of forming a diode, comprising:

forming a patterned insulative material over a base, the patterned insulative material having at least one opening extending therethrough to the base;

forming electrically conductive material as a liner within the at least one opening;

etching the liner to form the projections to form two or more projections extending upwardly from the base, said projections being spaced from one another by at least one gap that extends to an upper surface of the base;

depositing one or more layers across the projections and within the at least one gap to form the first electrode of the diode; and

forming a second electrode over said one or more layers to form the diode.

2. The method of claim 1 wherein the etching the liner comprises anisotropically etching the lining.

3. The method of claim 1 wherein forming the liner comprises atomic layer deposition.

4. The method of claim 1 wherein the one or more pedestals are comprised of the same composition as the base.

5. The method of claim 1 wherein the one or more pedestals comprise at least one composition that is not comprised by the base.

6. The method of claim 1 wherein the conformally depositing the one or more layers comprises atomic layer deposition.

7. The method of claim 1 wherein the one or more layers are at least two layers.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →