Apparatus and methods for transceiver interface overvoltage clamping
Apparatus and methods for transceiver interface overvoltage clamping are provided. In certain configurations, an interface device includes a first p-type well region and a second p-type well region in an n-type isolation structure. Additionally, the clamp device includes a first p-type active region and a first n-type active region in the first p-type well region and electrically connected to a first terminal of the clamp device. Furthermore, the clamp device includes a second p-type active region and a second n-type active region in the second p-type well region and electrically connected to a second terminal of the clamp device. The n-type isolation structure is in a p-type region of a semiconductor substrate, and electrically isolates the first and second p-type well regions from the p-type substrate region. The clamp device further includes a blocking voltage tuning structure positioned between the first and second n-type active regions.
1. An apparatus comprising:
an n-type isolation structure in a p-type region of a substrate;
a first p-type well region in the n-type isolation structure;
a first p-type active region and a first n-type active region in the first p-type well region, wherein the first n-type active region and the first p-type active region are electrically connected to a first terminal;
a second p-type well region in the n-type isolation structure and spaced apart from the first p-type well region, wherein the n-type isolation structure electrically isolates the first and second p-type well regions from the p-type region of the substrate;
a second p-type active region and a second n-type active region in the second p-type well region, wherein the second n-type active region and the second p-type active region are electrically connected to a second terminal; and
a blocking voltage tuning structure positioned between the first and second n-type active regions.
2. The apparatus of claim 1 , wherein the blocking voltage tuning structure comprises:
a first blocking junction comprising a first semiconductor interface between the first p-type well region and a first n-type region, wherein a reverse protection characteristic between the first and second terminals is based on a blocking voltage of the first blocking junction; and
a second blocking junction comprising a second semiconductor interface between the second p-type well region and a second n-type region, wherein a forward protection characteristic between the first and second terminals is based on a blocking voltage of the second blocking junction.
3. The apparatus of claim 1 , wherein the n-type isolation structure comprises a first n-type well that comprises a first wall of the n-type isolation structure, a second n-type well that comprises a second wall of the n-type isolation structure, and a deep n-type well isolation region that comprises a bottom of the n-type isolation structure.
4. The apparatus of claim 1 , wherein the blocking voltage tuning structure comprises:
a third n-type active region, wherein at least a portion of the third n-type active region is in the first p-type well region; and
a third p-type active region, wherein at least a portion of the third p-type active region is in the second p-type well region.
5. The apparatus of claim 4 , wherein the blocking voltage tuning structure further comprises:
an n-type well abutting the first p-type well region, wherein the third n-type active region is positioned along a boundary between the first p-type well region and the n-type well.
6. The apparatus of claim 4 , wherein the blocking voltage tuning structure further comprises:
an n-type lightly doped drain (NLDD) region beneath the third n-type active region.
7. The apparatus of claim 4 , wherein the blocking voltage tuning structure further comprises:
an oxide region extending between the third n-type active region and the third p-type active region.
8. The apparatus of claim 4 , wherein the blocking voltage tuning structure further comprises:
a dielectric region over a portion of the substrate between the third p-type active region and the third n-type active region; and
a conductor over the dielectric region.
9. The apparatus of claim 4 , wherein the blocking voltage tuning structure further comprises:
a fourth p-type active region positioned between the third p-type active region and the third n-type active region.
10. The apparatus of claim 4 , wherein the blocking voltage tuning structure further comprises:
a first oxide region adjacent to the third n-type active region; and
a second oxide region adjacent to the third p-type active region, wherein the first oxide region is spaced apart from the second oxide region.
11. The apparatus of claim 1 , wherein the first p-type well region comprises at least one of a first p-type well or a first shallow p-type well, and wherein the second p-type well region comprises at least one of a second p-type well or a second shallow p-type well.
12. The apparatus of claim 1 , wherein the blocking voltage tuning structure comprises:
a third p-type active region, wherein at least a portion of the third p-type active region is in the first p-type well region; and
a fourth p-type active region, wherein at least a portion of the fourth p-type active region is in the second p-type well region.
13. The apparatus of claim 12 , wherein the blocking voltage tuning structure further comprises:
a first dielectric region over a portion of the substrate between the third p-type active region and the fourth p-type active region; and
a first conductor over the first dielectric region.
14. The apparatus of claim 12 , wherein the blocking voltage tuning structure further comprises:
an n-type well positioned between the first p-type well region and the second p-type well region.
15. The apparatus of claim 12 , wherein the blocking voltage tuning structure further comprises:
a p-type lightly doped drain (PLDD) region beneath the third p-type active region.
16. The apparatus of claim 12 , wherein the blocking voltage tuning structure further comprises:
an oxide region positioned between the third p-type active region and the fourth p-type active region.
17. The apparatus of claim 12 , wherein the blocking voltage tuning structure further comprises:
a third n-active region positioned between the third p-type active region and the fourth p-type active region.
18. The apparatus of claim 17 , wherein the blocking voltage tuning structure further comprises:
a first dielectric region over a portion of the substrate between the third p-type active region and the third n-active region;
a first conductor over the first dielectric region;
a second dielectric region over a portion of the substrate between the fourth p-type active region and the third n-type active region; and
a second conductor over the second dielectric region.
19. The apparatus of claim 1 , wherein the blocking voltage tuning structure comprises:
an n-type well positioned between the first p-type well region and the second p-type well region.
20. The apparatus of claim 19 ,
wherein the first p-type well region comprises a first shallow p-type well abutting the n-type well on a first side; and
wherein the second p-type well region comprises a second shallow p-type well abutting the n-type well on a second side.
21. The apparatus of claim 20 ,
wherein the first p-type well region further comprises a first p-type well offset from the first shallow p-type well, wherein the first p-type well is spaced apart from the n-type well, and
wherein the second p-type well region further comprises a second p-type well offset from the second shallow p-type well, wherein the second p-type well is spaced apart from the n-type well.
22. The apparatus of claim 20 , wherein the blocking voltage tuning structure further comprises:
a first dielectric region over a boundary between the first shallow p-type well and the n-type well; and
a first conductor over the first dielectric region;
a second dielectric region over a boundary between the second shallow p-type well and the n-type well; and
a second conductor over the second dielectric region.
23. The apparatus of claim 22 , wherein the blocking voltage tuning structure further comprises:
at least one active region in the n-type well positioned between the first conductor and the second conductor.
24. The apparatus of claim 1 , wherein the n-type isolation structure comprises a first high voltage n-type well (HVNW) that operates as a first wall of the n-type isolation structure, a second HVNW that operates as a second wall of the n-type isolation structure, and an n-type buried layer isolation region that operates as a bottom of the n-type isolation structure.
25. The apparatus of claim 1 , wherein the blocking voltage tuning structure comprises:
a first blocking junction comprising a first semiconductor interface between the first p-type well region and a first n-type region;
a second blocking junction comprising a second semiconductor interface between the second p-type well region and a second n-type region, wherein a forward protection characteristic between the first and second terminals is based on a blocking voltage of the second blocking junction; and
a PNPN silicon controlled rectifier (SCR) configured to bypass the first blocking junction, wherein a reverse protection characteristic between the first and second terminals is controlled by the PNPN SCR.
26. The apparatus of claim 1 , wherein the first p-type well region comprises at least a first high voltage p-type well (HVPW), and wherein the second p-type well region comprises at least a second HVPW.
27. The apparatus of claim 26 , wherein the blocking voltage tuning structure comprises:
a HVNW positioned between the first HVPW and the second HVPW;
a first n-type well positioned in the first HVPW;
a third p-type active region positioned in the first n-type well and electrically connected to the HVNW via metallization, wherein the third p-type active region, the first n-type well, the first p-type well region, and the first n-type active region operate as a PNPN silicon controlled rectifier.
28. The apparatus of claim 27 , wherein the first p-type well region further comprises at least one of a first p-type well or a first shallow p-type well abutting the first n-type well.
29. The apparatus of claim 27 , wherein the blocking voltage tuning structure further comprises:
a third n-type active region positioned in the first n-type well; and
a fourth n-type active region in the HVNW, wherein the third p-type active region and the fourth n-type active region are electrically connected to one another via metallization.
30. The apparatus of claim 29 , wherein the blocking voltage tuning structure further comprises:
a fifth n-type active region in the HVNW;
a dielectric region over the HVNW between the fourth n-type active region and the fifth n-type active region; and
a conductor over the dielectric region.
31. The apparatus of claim 29 , wherein the third p-type active region and the third n-type active region are electrically connected to one another via metallization.
32. The apparatus of claim 27 , wherein the first p-type well region further comprises a first p-type well abutting the first n-type well, wherein the blocking voltage tuning structure further comprises:
a dielectric region over a boundary between the first p-type well and the first n-type well; and
a conductor over the dielectric region.
33. The apparatus of claim 27 , wherein the blocking voltage tuning structure comprises:
a third n-type active region positioned in the first n-type well; and
a fourth n-type active region in the HVNW, wherein the third p-type active region and the fourth n-type active region are electrically connected to one another via metallization.
34. The apparatus of claim 1 , further comprising a p-type guard ring surrounding a plurality of sides of the n-type isolation structure, wherein the p-type guard ring does not abut the n-type isolation structure.
35. An apparatus comprising:
an n-type isolation structure in a p-type region of a substrate;
a first p-type well region in the n-type isolation structure;
a first p-type active region and a first n-type active region in the first p-type well region, wherein the first n-type active region and the first p-type active region are electrically connected to a first terminal;
a second p-type well region in the n-type isolation structure and spaced apart from the first p-type well region, wherein the n-type isolation structure electrically isolates the first and second p-type well regions from the p-type region of the substrate;
a second p-type active region and a second n-type active region in the second p-type well region, wherein the second n-type active region and the second p-type active region are electrically connected to a second terminal; and
a means for blocking voltage tuning positioned between the first and second n-type active regions.