IP Library Granted Patent US 9,735,204
Granted Patent B2
US 9,735,204 · App. 14/553,559 · Granted Aug 15, 2017

Solid-state imaging device and method for manufacturing the same

Inventors: Ryota Sakaida (Osaka, JP); Nobuyoshi Takahashi (Toyama, JP); Kosaku Saeki (Osaka, JP)
Assignee: Panasonic Intellectual Property Management Co., Ltd.
H01L27/307H01L21/28525H01L21/76889H01L21/76895H01L23/485H01L27/14612H01L27/14643H01L51/441H01L21/76897H01L2924/0002
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Quick Facts
Patent No.
US 9,735,204
App. No.
14/553,559
Granted
Aug 15, 2017
Kind
B2
Abstract

Each imaging pixel provided in a solid-state imaging device includes a charge accumulation part which is a diffusion region formed in a substrate, a gate electrode formed lateral to the charge accumulation part on the substrate, an insulating film formed on the charge accumulation part, and a contact plug connected to the charge accumulation part so as to penetrate the insulating film and made of semiconductor. The contact plug is, at a lower part thereof, embedded in the insulating film, and is, at an upper part thereof, exposed through the insulating film. Silicide is formed on the upper part of the contact plug, and the charge accumulation part and the gate electrode are covered by the insulating film.

Claims (74)

1. A solid-state imaging device comprising:

an imaging pixel region where a plurality of imaging pixels are arranged on a substrate, wherein

each imaging pixel includes

a diffusion region formed in the substrate,

a first gate electrode formed lateral to the diffusion region on the substrate,

a first insulating film formed on the diffusion region and the first gate electrode,

a first contact plug connected to the diffusion region so as to penetrate the first insulating film and made of semiconductor,

a second contact plug connected to the first gate electrode so as to penetrate the first insulating film and made of a material identical to the semiconductor forming the first contact plug,

the first contact plug is, at a lower part thereof, embedded in the first insulating film, and is, at an upper part thereof, exposed through the first insulating film,

the second contact plug is, at a lower part thereof, embedded in the first insulating film, and is, at an upper part thereof, exposed through the first insulating film,

silicide is formed on the upper part of the first contact plug and the upper part of the second contact plug,

a solid-state imaging device further comprises a photoelectric conversion layer formed above the diffusion region, and

the diffusion region is a charge accumulation part.

2. The solid-state imaging device of claim 1 , wherein a peripheral edge part of the upper part of the first contact plug is formed so as to extend over the first insulating film.

3. The solid-state imaging device of claim 1 , wherein the diffusion region forms a pMOS transistor.

4. The solid-state imaging device of claim 1 , wherein the semiconductor is boron-doped polysilicon.

5. The solid-state imaging device of claim 1 , further comprising:

a sidewall formed on one of side surfaces of the first gate electrode; and

a second insulating film formed so as to extend from the other side surface of the first gate electrode close to the diffusion region to above the diffusion region,

wherein the second insulating film is, on the diffusion region, formed between the diffusion region and the first insulating film, and

the first contact plug penetrates the second insulating film.

6. The solid-state imaging device of claim 5 , wherein

the sidewall is formed of a multilayer film in which at least two insulating films are stacked on each other, and

the second insulating film is one of the insulating films forming the multilayer film.

7. The solid-state imaging device of claim 1 , wherein a contact diameter of the first contact plug at the lower part thereof is smaller than that of the second contact plug at the lower part thereof.

8. The solid-state imaging device of claim 1 , wherein a center bottom part of the lower part of the first contact plug is embedded in a recessed part formed in the diffusion region.

9. The solid-state imaging device of claim 1 , wherein the first and second contact plugs are of unitary construction.

10. The solid-state imaging device of claim 1 , further comprising:

another diffusion region adjacent to the diffusion region;

the first insulating film formed on the another diffusion region; and

a third contact plug connected to the another diffusion region so as to penetrate the first insulating film,

wherein the third contact plug is made of a material identical to the semiconductor forming the first and second contact plugs,

the third contact plug is, at a lower part thereof, embedded in the first insulating film, and is, at an upper part thereof, exposed through the first insulating film,

silicide is formed on the upper part of the third contact plug, and

the first and third contact plugs are of unitary construction.

11. The solid-state imaging device of claim 1 , further comprising:

a contact formed on the first contact plug and having conductivity,

wherein the photoelectric conversion layer is electrically connected to the charge accumulation part through the first contact plug and the contact.

12. The solid-state imaging device of claim 1 , wherein

the diffusion region, the first gate electrode, and the first contact plug contain silicon as a main component.

13. A solid-state imaging device comprising:

an imaging pixel region where a plurality of imaging pixels are arranged on a substrate,

wherein each imaging pixel includes

a diffusion region formed in the substrate,

a first gate electrode formed lateral to the diffusion region on the substrate,

a first insulating film formed on the diffusion region, and

a first contact plug connected to the diffusion region so as to penetrate the first insulating film and made of semiconductor,

the first contact plug is, at a lower part thereof, embedded in the first insulating film, and is, at an upper part thereof, exposed through the first insulating film,

silicide is formed on the upper part of the first contact plug, and

the diffusion region and the first gate electrode are covered by the first insulating film,

the solid-state imaging device further comprises:

a second gate electrode formed on the substrate in a region opposite to the first gate electrode relative to the diffusion region; and

a contact formed on the first contact plug and having conductivity, wherein

part of an upper lateral part of the first contact plug is positioned on a sidewall formed above or lateral to the first gate electrode,

the remaining part of the upper lateral part of the first contact plug is positioned on a sidewall formed above or lateral to the second gate electrode,

a recessed part is formed at an upper part of the first contact plug above the diffusion region, and

the contact is connected to the recessed part formed at the upper part of the first contact plug.

14. A method for manufacturing a solid-state imaging device including an imaging pixel region where a plurality of imaging pixels are arranged on a substrate, the method comprising:

a step of forming a diffusion region corresponding to each imaging pixel in the imaging pixel region in the substrate;

a step of forming an insulating film on the diffusion region;

a step of forming, in the insulating film, a first hole through which the diffusion region is exposed;

a step of forming a semiconductor film on the insulating film such that the first hole is filled with the semiconductor film;

a step of forming, from the semiconductor film, a first contact plug filling the first hole and exposed through the insulating film; and

a step of forming silicide on the first contact plug exposed through the insulating film, wherein

a peripheral edge part of an upper part of the first contact plug is formed so as to extend over the insulating film,

the method further includes a step of forming, before the step of forming the insulating film, a gate electrode lateral to the diffusion region on the substrate,

wherein the step of forming the first hole includes a step of forming a second hole through which the gate electrode is exposed,

the step of forming the first contact plug includes a step of forming, from the semiconductor film, a second contact plug filling the second hole and exposed through the insulating film,

at the step of forming the silicide, silicide is simultaneously formed on the second contact plug exposed through the insulating film, and

a peripheral edge part of an upper part of the second contact plug extends over the insulating film.

15. The method of claim 14 , wherein

at the step of forming the first contact plug, at least part of a region, where the first contact plug is not formed, of the insulating film in a thickness direction thereof remains.

16. The method of claim 14 , wherein

the diffusion region and the first contact plug contain silicon as a main component.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 24, 2014
From: SAKAIDA, RYOTA; TAKAHASHI, NOBUYOSHI; SAEKI, KOSAKU
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 034585/0579 →
Priority Claims (1)
JP 2012-139899 · Jun 21, 2012 · national
Continuity (2)
Continuation PCTJP2013002750 · Apr 23, 2013
Related Publication 20150076500A1 · Mar 19, 2015