Semiconductor device including a clock adjustment circuit

1. An apparatus comprising:

a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals; and

a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to adjust a frequency of a cycle of producing the first control signal to initiate the phase control operation.

2. The apparatus as claimed in claim 1 , wherein the phase control operation is performed in a manner of a DLL (Delay Locked Loop).

3. The apparatus as claimed in claim 1 , wherein the timing generator includes an enable signal generator that is configured to initiate the phase control operation responsive to a timing signal being activated and terminate the phase control operation responsive to the second control signal indicating that the first and second clock signals are in phase.

4. The apparatus as claimed in claim 3 , wherein the second control signal indicates, by changing a logic state thereof between first and second logic levels, that the first and second clock signals are in phase.

5. The apparatus as claimed in claim 3 , wherein the timing generator includes a detector that is configured to activate a third control signal when the second control signal indicates that the first and second clock signals are out of phase over a period that includes a plurality of consecutive pulses of the first clock signal.

6. The apparatus as claimed in claim 5 , wherein the second control signal indicates, by keeping a logic state thereof unchanged, that the first and second clock signals are out of phase over the period that includes a plurality of consecutive pulses of the first clock signal.

7. An apparatus comprising:

a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal that indicates, by keeping a logic state thereof unchanged, that the first and second clock signals are out of phase over the period that includes a plurality of consecutive pulses of the first clock signal; and

a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal, wherein the timing generator includes an enable signal generator that is configured to initiate the phase control operation responsive to a timing signal being activated and terminate the phase control operation responsive to the second control signal indicating that the first and second clock signals are in phase and further includes a detector that is configured to activate a third control signal when the second control signal indicates that the first and second clock signals are out of phase over a period that includes a plurality of consecutive pulses of the first clock signal, wherein the enable signal generator is configured to produce the first control signal in a first cycle during the third control signal being activated and in a second cycle during the third control signal being deactivated.

8. The apparatus as claimed in claim 7 , wherein the first cycle is smaller than the second cycle.

9. An apparatus comprising:

a DLL (Delayed Locked Loop) circuit configured to perform a DLL operation on first and second clock signals, the DLL circuit configured to initiate the DLL operation each time a first control signal is asserted, the DLL circuit including a phase comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals; and

a timing generator configured to make, after making a first assertion of the first control signal, a second assertion of the first control signal in a selected one of first and second time periods, the first time period longer than the second time period, a selection of the first time period or the second time period being made based on a period of time during which the first and second clock signals are being out of phase in the DLL operation as indicated by the second control signal.

10. The apparatus as claimed in claim 9 , wherein the DLL circuit is configured to terminate the DLL operation responsive to the second control signal indicating that the first and second clock signals are in phase.

11. The apparatus as claimed in claim 10 , wherein the timing generator is configured to detect a period of time during which the first and second clock signals are out of phase.

12. An apparatus comprising:

a DLL (Delayed Locked Loop) circuit configured to perform a DLL operation on first and second clock signals, the DLL circuit configured to initiate the DLL operation each time a first control signal is asserted, the DLL circuit including a phase comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, the DLL circuit further configured to terminate the DLL operation responsive to the second control signal indicating that the first and second clock signals are in phase; and

a timing generator configured to detect a period of time during which the first and second clock signals are out of phase and further configured to make, after making a first assertion of the first control signal, a second assertion of the first control signal in a selected one of first and second time periods, the first and second time periods being different from each other, a selection of the first time period or the second time period being made responsive to the second control signal, wherein the first time period is larger than the second time period and the second assertion of the first control signal is made in the first time period when the period of time in the DLL operation responsive to the first assertion of the first control signal is detected to be equal or smaller than a first value, and the second assertion of the first control signal is made in the second time period when the period of time in the DLL operation responsive to the first assertion of the first control signal is detected to be larger than the first value.

13. The apparatus as claimed in claim 12 , wherein the first value corresponds to a period that includes a plurality of consecutive pulses of the first clock signal.

14. The apparatus as claimed in claim 13 , wherein the first clock signal is supplied from outside of the apparatus and the second clock signal is produced inside of the apparatus.

15. An apparatus comprising:

a DLL (Delayed Locked Loop) circuit configured to perform a DLL operation on first and second clock signals, the DLL circuit configured to initiate the DLL operation each time a first control signal is asserted, the DLL circuit including a phase comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals; and

a timing generator configured to make, after making a first assertion of the first control signal, a second assertion of the first control signal in a selected one of first and second time periods, the first and second time periods being different from each other, a selection of the first time period or the second time period being made responsive to the second control signal, wherein the first time period is larger than the second time period and the second assertion of the first control signal is made in the first time period when a period of time during which the first and second clock signals are being out of phase in the DLL operation responsive to the first assertion of the first control signal is detected to be equal or smaller than a first value, and the second assertion of the first control signal is made in the second time period when the period of time is detected to be larger than the first value.

16. A method comprising:

making a first assertion of a first control signal;

initiating a first phase control operation to control a phase relationship between first and second clock signals responsive to the first assertion of the first control signal;

terminating the first phase control operation when the first and second clock signals are in phase;

making a second assertion of the first control signal after a first time period when a condition in which the first and second clock signals are out of phase in the first phase control operation continues over a first period, and after a second time period when the condition ends within the first period, wherein the second time period is longer than the first time period; and

initiating a second phase control operation to control a phase relationship between the first and second clock signals responsive to the second assertion of the first control signal.

17. The method as claimed in claim 16 , wherein each of the first and second phase control operation is performed in a DLL (Delay Locked Loop) manner.

18. The method as claimed in claim 17 , wherein the first time period is smaller than the second time period.

19. The method as claimed in claim 18 , wherein the method comprises:

producing a second control signal indicative of a phase difference between the first and second clock signals; and

judging a state of the second control signal to detect whether the first and second clock signals are in phase or out of phase.

20. The method as claimed in claim 19 , wherein the second control signal takes a first state to indicate the first and second clock signals are in phase and a second state to indicate the first and second clock signals are out of phase.