Solid-state imaging device and manufacturing method therefor

1. A solid-state imaging device comprising:

a plurality of pixels, the pixel including

a photoelectric conversion unit,

a floating diffusion region,

an amplifying transistor configured to output a signal based on an amount of electric charge generated by the photoelectric conversion unit, and

a resetting transistor configured to reset an input node of the amplifying transistor;

a first substrate; and

a second substrate,

wherein a first insulating film is provided on a first principal surface of the first substrate,

wherein the first substrate includes a first pixel region;

wherein a plurality of photoelectric conversion units are arranged in the first pixel region;

wherein a first element isolation portion is provided in the first pixel region, configured to electrically isolate the plurality of photoelectric conversion units;

wherein a second insulating film is provided on the second substrate;

wherein the second substrate includes a second pixel region;

wherein a plurality of the amplifying transistors and a plurality of the resetting transistors are arranged in the second pixel region;

wherein a second element isolation portion is provided in the second pixel region, configured to electrically isolate at least a part of the plurality of the amplifying transistors and at least a part of the plurality of the resetting transistors;

wherein an interface of a region where the first element isolation portion is provided, between the first substrate and the first insulating film, is arranged at a first depth with respect to an interface of a region where the photoelectric conversion unit is arranged, between the first substrate and the first insulating film;

wherein an interface of a region where the second element isolation portion is provided, between the second substrate and the second insulating film, is arranged at a second depth with respect to an interface of a region where the amplifying transistor is arranged, between the second substrate and the second insulating film; and

wherein the first depth is shallower than the second depth.

2. The solid-state imaging device according to claim 1 , wherein light is incident on the first substrate from a second principal surface side thereof, the second principal surface being opposite to the first principal surface of the first substrate.

3. The solid-state imaging device according to claim 1 , wherein the second element isolation portion is one of LOCOS isolation and STI isolation.

4. The solid-state imaging device according to claim 1 , wherein the first element isolation portion is one of PN isolation, mesa-type insulator isolation, and EDI isolation.

5. The solid-state imaging device according to claim 1 , wherein at least two of the plurality of pixels share the floating diffusion region.

6. The solid-state imaging device according to claim 1 , wherein the floating diffusion regions are provided at a pitch of 3 micrometers or less.

7. A solid-state imaging device comprising:

a plurality of pixels, the pixel including

a photoelectric conversion unit,

a floating diffusion region,

a transferring transistor including a transferring gate electrode configured to transfer signal charge generated at the photoelectric conversion unit to the floating diffusion region,

an amplifying transistor configured to output a signal based on an amount of electric charge of the floating diffusion region, and

a resetting transistor configured to reset a voltage of the floating diffusion region;

a signal processing circuit for processing a signal output from the plurality of pixels;

a first semiconductor substrate; and

a second semiconductor substrate,

wherein a first insulating film is provided on a first principal surface of the first semiconductor substrate,

wherein the first semiconductor substrate includes a pixel region;

wherein a plurality of photoelectric conversion units and a plurality of floating diffusion regions are arranged in the pixel region;

wherein a first element isolation portion is provided in the pixel region, configured to electrically isolate at least a part of the plurality of photoelectric conversion units and at least a part of the plurality of floating diffusion regions;

wherein a second insulating film is provided on the second semiconductor substrate;

wherein the second semiconductor substrate includes a circuit region;

wherein a plurality of transistors included in the signal processing circuit are arranged in the circuit region;

wherein a second element isolation portion is arranged in the circuit region, configured to electrically isolate at least a part of the plurality of transistors;

wherein an interface of a region where the first element isolation portion is provided, between the first semiconductor substrate and the first insulating film, is arranged at a first depth with respect to an interface of a region where the photoelectric conversion unit is arranged, between the first semiconductor substrate and the first insulating film;

wherein an interface of a region where the second element isolation portion is provided, between the second semiconductor substrate and the second insulating film, is arranged at a second depth with respect to an interface of a region where the transistor included in the signal processing circuit is arranged, between the second semiconductor substrate and the second insulating film; and

wherein the first depth is shallower than the second depth.

8. The solid-state imaging device according to claim 7 , wherein light is incident on the first semiconductor substrate from a second principal surface side thereof, the second principal surface being opposite to the first principal surface of the first semiconductor substrate.

9. The solid-state imaging device according to claim 8 , further comprising:

an electrically-conductive pattern configured to electrically connect the floating diffusion region and a gate electrode of the amplifying transistor,

wherein the first principal surface of the first semiconductor substrate faces a principal surface of the second semiconductor substrate on which the gate electrode of the amplifying transistor is arranged, the electrically-conductive pattern being interposed therebetween.

10. The solid-state imaging device according to claim 8 ,

wherein the first semiconductor substrate has a thickness where a part of the light reaches the first principal surface of the first semiconductor substrate.

11. The solid-state imaging device according to claim 7 , wherein the first element isolation portion is one of PN isolation, mesa-type insulator isolation, and EDI isolation, and

wherein the second element isolation portion is one of LOCOS isolation and STI isolation.

12. The solid-state imaging device according to claim 7 ,

wherein the first principal surface of the first semiconductor substrate includes a (100)-surface.

13. The solid-state imaging device according to claim 7 ,

wherein the plurality of pixels form a matrix including a plurality of pixel columns, and

wherein the signal processing circuit includes a plurality of column circuits respectively corresponding to the plurality of pixel columns.

14. The solid-state imaging device according to claim 13 ,

wherein the column circuit includes an analog-to-digital convertor.

15. The solid-state imaging device according to claim 7 ,

wherein the photoelectric conversion unit includes

a first semiconductor region of a first conductivity type configured to collect a signal charge,

a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first principal surface of the first semiconductor substrate, and

a third semiconductor region of the second conductivity type provided between the first semiconductor region and a second principal surface being opposite to the first principal surface of the first semiconductor substrate.

16. The solid-state imaging device according to claim 15 ,

wherein the first, second and third semiconductor regions forms an embedded-type photodiode.

17. The solid-state imaging device according to claim 15 ,

wherein the floating diffusion region has a higher impurity concentration than an impurity concentration of the first semiconductor region.

18. The solid-state imaging device according to claim 15 ,

wherein the second semiconductor region has a higher impurity concentration than an impurity concentration of the first element isolation portion.

19. The solid-state imaging device according to claim 7 ,

wherein the transferring transistor includes a channel region implanted with a channel impurity.

20. The solid-state imaging device according to claim 7 ,

wherein a negative voltage is applied to the transferring gate electrode during an exposure time period.

21. The solid-state imaging device according to claim 7 ,

the transistor included in the signal processing circuit includes a silicide formed thereon.

22. The solid-state imaging device according to claim 7 ,

wherein the first element isolation portion includes a PN isolation, and

wherein a reverse bias voltage is applied to a PN junction of the PN isolation.

23. The solid-state imaging device according to claim 22 , further comprising:

a contact plug configured to supply the reverse bias voltage to the PN isolation.

24. The solid-state imaging device according to claim 7 ,

wherein the first semiconductor substrate is formed by an epitaxial growth method.

25. The solid-state imaging device according to claim 7 , further comprising:

a light shielding portion provided on a second principal surface being opposite to the first principal surface of the first semiconductor substrate;

a color filter provided on the second principal surface; and

a microlens provided on the second principal surface.

26. The solid-state imaging device according to claim 7 ,

wherein light is incident on the first semiconductor substrate from a second principal surface side thereof, the second principal surface being opposite to the first principal surface of the first semiconductor substrate, and

wherein the photoelectric conversion unit includes

a first semiconductor region of a first conductivity type configured to collect a signal charge,

a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first principal surface of the first semiconductor substrate, and

a third semiconductor region of the second conductivity type provided between the first semiconductor region and the second principal surface of the first semiconductor substrate.

27. The solid-state imaging device according to claim 26 ,

wherein the floating diffusion region has a higher impurity concentration than an impurity concentration of the first semiconductor region, and

wherein the second semiconductor region has a higher impurity concentration than an impurity concentration of the first element isolation portion.

28. The solid-state imaging device according to claim 27 ,

wherein the plurality of pixels form a matrix including a plurality of pixel columns, and

wherein the signal processing circuit includes a plurality of analog-to-digital converters respectively corresponding to the plurality of pixel columns.

29. The solid-state imaging device according to claim 28 ,

wherein the first principal surface of the first semiconductor substrate includes a (100)-surface.

30. The solid-state imaging device according to claim 29 ,

the transistor included in the signal processing circuit includes a silicide formed thereon.

31. The solid-state imaging device according to claim 30 ,

wherein the first element isolation portion includes a PN isolation,

wherein a reverse bias voltage is applied to a PN junction of the PN isolation, and

wherein the solid-state imaging device further comprises a contact plug configured to supply the reverse bias voltage to the PN isolation.

32. The solid-state imaging device according to claim 31 ,

wherein the first semiconductor substrate has a thickness where a part of the light reaches the first principal surface of the first semiconductor substrate.

33. The solid-state imaging device according to claim 32 , further comprising:

a light shielding portion provided on the second principal surface of the first semiconductor substrate;

a color filter provided on the second principal surface; and

a microlens provided on the second principal surface.