Method for forming a self-aligned contact in a damascene structure used to form a memory device
View Patent ↗Exemplary embodiments of the present invention are directed towards a method for fabricating a self-aligned contact under a bitline in a damascene structure for a memory device comprising forming a dummy pattern, forming dielectric sidewalls using a first dielectric film around the dummy pattern, forming a second dielectric film around the dielectric sidewalls, removing the dummy pattern forming a plurality of trenches, depositing active cell material in each of the plurality of trenches, forming a third dielectric film atop the active cell material; and creating a self-aligned contact hole using etch selectivity between the dielectric sidewalls and the second dielectric film.
1. A method for fabricating a self-aligned contact in a damascene structure comprising:
forming a dummy pattern;
forming dielectric sidewalls using a first dielectric film around the dummy pattern;
forming a second dielectric film on the dielectric sidewalls;
removing the dummy pattern, thereby forming a plurality of first trenches;
depositing active cell material and etching back to form active cells in each of the plurality of trenches;
forming a third dielectric film atop the active cells;
forming a fourth dielectric film atop the second and third dielectric films, wherein an etching rate of the first and third dielectric films is less than an etching rate of the second and fourth dielectric films; and
creating a self-aligned contact hole by etching the second and forth dielectric films.
2. The method of claim 1 wherein the self-aligned contact hole is a bitline contact coupled to a bitline for a memory device.
3. The method of claim 2 , wherein the bitline contact is deposited under the bitline.
4. The method of claim 2 wherein the dummy pattern is composed of polysilicon.
5. The method of claim 2 , wherein the dielectric sidewalls and the third dielectric film are composed of Silicon Nitride.
6. The method of claim 1 , wherein the second dielectric film and the fourth dielectric film are composed of Silicon dioxide.
7. The method of claim 1 , wherein the etching rate of the second dielectric film is at least twenty times greater than the etching rate of the first dielectric film forming the dielectric sidewalls.
8. The method of claim 1 , wherein the active cell material is a resistive material.
9. The method of claim 8 , wherein the resistive material is one of HfOx, TiOx, NiOx, AlOx.
10. The method of claim 8 , wherein the resistive material consists of Cu, Ag, Te and other transition metals.
11. The method of claim 1 , wherein the active cell material is a capacitive material.
12. The method of claim 11 , wherein the capacitive material is a dielectric material.
13. The method of claim 1 , further comprising:
patterning a photo resist layer on the third dielectric film; and
removing the photo resist layer to create the self-aligned contact holes.
14. The method of claim 1 , further comprising:
depositing a photo resist layer on the fourth dielectric film, excluding a region above the self-aligned contact hole.
15. The method of claim 14 , further comprising:
removing the photo resist layer.
16. The method of claim 1 , further comprising:
depositing a conductive layer in the self-aligned contact hole; and
depositing a metal layer above the conductive layer to form a self-aligned contact.
17. The method of claim 16 , wherein depositing the conductive layer comprises:
depositing a titanium film (Ti);
depositing a titanium nitride (TiN) film; and
depositing a tungsten film atop the TiN film.