Methods for fabricating a memory device with an enlarged space between neighboring bottom electrodes

1. A method for fabricating a memory device comprising an enlarged space between neighboring bottom electrodes comprising:

depositing a poly-silicon layer on a substrate;

depositing a carbon layer above the poly-silicon layer;

patterning a photo-resist layer on the carbon layer,

depositing a first spacer layer on the photo-resist layer;

performing a modified photolithography process on the photo resist layer after etching back the first spacer layer creating sidewalls;

etching the sidewalls by using the sidewalls as a mask to create a photo-resist pattern;

depositing a second spacer layer on the carbon layer;

etching back the second spacer layer;

exhuming the carbon layer leaving pairs of carbon sidewalls;

performing an etching process to form trenches;

stripping all layers except the poly-silicon layer and the substrate, forming stacks topped with poly-silicon;

implanting a bottom electrode in each of the trenches; and

implanting a top electrode in each of the stacks.

2. The method of claim 1 further comprising:

depositing an oxide layer above the bottom electrodes; and

depositing active cell material on the oxide layer and neighboring top electrodes.

3. The method of claim 2 , further comprising:

removing the poly-silicon prior to implanting the top electrodes.

4. The method of claim 1 , wherein instead of modifying lithography conditions, the second spacer layer is thinned so when the second spacer layer is etched, a distance between a sidewall in neighboring carbon sidewalls is greater than a distance between each sidewall in a pair of carbon sidewalls to achieve a greater wordline width.

5. The method of claim 1 , wherein the first spacer layer and the second spacer layer are oxide layers.

6. The method of claim 1 , wherein the photo-resist is slimed after being patterned.

7. The method of claim 1 , wherein the photo-resist pattern is modified to overexpose the photo resist layer.

8. A method for fabricating a memory device comprising an enlarged space between neighboring bottom electrodes comprising:

depositing a poly-silicon layer on a substrate,

depositing a carbon layer above the poly-silicon layer;

patterning a photo-resist layer on the carbon layer, wherein after the photo-resist layer is patterned, the photo-resist layer is shrunk to achieve a greater wordline width; and

depositing a first spacer layer on the photo-resist layer.

9. The method of claim 8 , wherein shrinking is performed using a dry etching process.

10. The method of claim 9 , wherein shrinking is performed using a heating process.

11. A memory device comprising:

a plurality of memory cells coupled to a plurality of wordlines,

wherein a bottom electrode of a transistor coupled to each of the plurality of memory cells is spaced a predetermined distance away from a bottom electrode of a transistor coupled to a neighboring memory cell to prevent thermal disturbances.

12. The memory device of claim 11 , wherein a ratio of the width of the bottom electrode to the width of the distance between neighboring electrodes is 1.2 or greater.