Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor
Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.
1. A semiconductor memory cell comprising:
a plurality of bipolar devices; and
a common base region of a first conductivity type configured to store a charge that is indicative of a memory state of said semiconductor memory cell;
wherein adjacent ones of each of said bipolar devices are separated by a conductive region having a second conductivity type;
wherein said common base region is shared among said plurality of bipolar devices; and
wherein one of said plurality of bipolar devices is configured to maintain the charge stored in said common base region.
2. The semiconductor memory cell of claim 1 , wherein said common base region stores at least two stable charge levels.
3. The semiconductor memory cell of claim 1 , further comprising a plurality of gates.
4. The semiconductor memory cell of claim 1 , wherein the semiconductor memory cell includes ports, wherein a total number of said ports is equal to a total number of said bipolar devices.
5. The semiconductor memory cell of claim 1 , wherein the semiconductor memory cell includes a fin structure, and further wherein the fin structure includes the common base region.