IP Library Granted Patent US 9,179,082
Granted Patent B2
US 9,179,082 · App. 14/564,750 · Granted Nov 3, 2015

Solid-state imaging device and electronic apparatus

Inventors: Kazuichiro Itonaga (Tokyo, JP); Shizunori Matsumoto (Kanagawa, JP)
Assignee: SONY CORPORATION
H04N5/374H01L27/14603H01L27/14609H01L27/14612H01L27/14625H01L27/14627H01L27/14629H01L27/14641H01L27/14643H01L27/14831H04N5/357H04N5/378H04N5/3745H04N9/045H01L27/14607H01L27/14647
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Quick Facts
Patent No.
US 9,179,082
App. No.
14/564,750
Granted
Nov 3, 2015
Kind
B2
Abstract

A solid-state imaging device includes a layout in which one sharing unit includes an array of photodiodes of 2 pixels by 4×n pixels (where, n is a positive integer), respectively, in horizontal and vertical directions.

Claims (35)

1. A solid-state imaging device comprising:

a first structural unit including a first array of photodiodes of four first pixels in column and row directions, the first structural unit including:

a first floating diffusion;

four first transfer gates, each having a trapezoidal shape and arranged around the first floating diffusion; and

a second structural unit including a second array of photodiodes of four second pixels in column and row directions, the second structural unit including:

a second floating diffusion;

four second transfer gates, each having a trapezoidal shape and arranged around the second floating diffusion; and

an amplification transistor and a select transistor located between and interconnected to the first structural unit and the second structural unit.

2. The solid-state imaging device according to claim 1 , wherein the amplification transistor and the select transistor are disposed along a side of the first structural unit.

3. The solid-state imaging device according to claim 1 , further comprising a connection wiring that is connected to the amplification transistor and the first floating diffusion, the connection wiring being disposed in the column direction.

4. The solid-state imaging device according to claim 1 , further comprising a reset transistor power supply wire, a reset wire, and a readout wire that are disposed in the row direction.

5. The solid-state imaging device according to claim 1 , further comprising a vertical signal line and an amplification transistor power supply wire that are disposed in the column direction.

6. The solid-state imaging device according to claim 1 , further comprising dummy wirings that are disposed in the column direction and between at least two of the four first pixels that are adjacent to each other.

7. The solid-state imaging device according to claim 2 , further comprising a connection wiring that is connected to the amplification transistor and the first floating diffusion, the connection wiring being disposed in the column direction.

8. The solid-state imaging device according to claim 7 , further comprising a reset transistor power supply wire, a reset wire, and a readout wire that are disposed in the row direction.

9. The solid-state imaging device according to claim 8 , further comprising a vertical signal line and an amplification transistor power supply wire that are disposed in the column direction.

10. The solid-state imaging device according to claim 9 , further comprising dummy wirings that are disposed in the column direction and between at least two of the four first pixels that are adjacent to each other.

11. An electronic apparatus comprising:

a solid-state imaging device including:

a first structural unit including a first array of photodiodes of four first pixels in column and row directions, the first structural unit including:

a first floating diffusion;

four first transfer gates, each having a trapezoidal shape and arranged around the first floating diffusion; and

a second structural unit including a second array of photodiodes of four second pixels in column and row directions, the second structural unit including:

a second floating diffusion;

four second transfer gates, each having a trapezoidal shape and arranged around the second floating diffusion; and

an amplification transistor and a select transistor located between and interconnected to the first structural unit and the second structural unit.

12. The electronic apparatus according to claim 11 , wherein the amplification transistor and the select transistor are disposed along a side of the first structural unit.

13. The electronic apparatus according to claim 11 , further comprising a connection wiring that is connected to the amplification transistor and the first floating diffusion, the connection wiring being disposed in the column direction.

14. The electronic apparatus according to claim 11 , further comprising a reset transistor power supply wire, a reset wire, and a readout wire that are disposed in the row direction.

15. The electronic apparatus according to claim 11 , further comprising a vertical signal line and an amplification transistor power supply wire that are disposed in the column direction.

16. The electronic apparatus according to claim 11 , further comprising dummy wirings that are disposed in the column direction and between at least two of the four first pixels that are adjacent to each other.

17. The electronic apparatus according to claim 12 , further comprising a connection wiring that is connected to the amplification transistor and the first floating diffusion, the connection wiring being disposed in the column direction.

18. The electronic apparatus according to claim 17 , further comprising a reset transistor power supply wire, a reset wire, and a readout wire that are disposed in the row direction.

19. The electronic apparatus according to claim 18 , further comprising a vertical signal line and an amplification transistor power supply wire that are disposed in the column direction.

20. The electronic apparatus according to claim 19 , further comprising dummy wirings that are disposed in the column direction and between at least two of the four first pixels that are adjacent to each other.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2020
From: ITONAGA, KAZUICHIRO; MATSUMOTO, SHIZUNORI
To: SONY CORPORATION
Reel/Frame 052198/0044 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2020
From: ITONAGA, KAZUICHIRO; MATSUMOTO, SHIZUNORI
To: SONY CORPORATION
Reel/Frame 052206/0398 →
Priority Claims (1)
JP 2009-006892 · Jan 15, 2009 · national
Continuity (4)
Continuation 14107839 · Dec 16, 2013
Division 13609596 · Sep 11, 2012
Division 12684445 · Jan 8, 2010
Related Publication 20150092094A1 · Apr 2, 2015