IP Library › Granted Patent US 9,236,386
Granted Patent B2
US 9,236,386 · App. 14/565,222 · Granted Jan 12, 2016

Semiconductor device with buried bit line and method for fabricating the same

Inventors: Heung-Jae Cho (Gyeonggi-do, KR); Eui-Seong Hwang (Gyeonggi-do, KR); Eun-Shil Park (Gyeonggi-do, KR)
Assignee: SK Hynix Inc.
H01L27/10814H01L21/8239H01L27/0629H01L27/10876H01L27/10885H01L29/41741H01L29/66666H01L29/7827H01L29/456
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,236,386
App. No.
14/565,222
Granted
Jan 12, 2016
Kind
B2
Abstract

A method for fabricating a semiconductor device includes etching a semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate; forming a supporter in each of the bulb-type trenches; dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and forming a bit line in each body line of the pair of body lines.

Claims (19)

1. A semiconductor device comprising:

a semiconductor substrate;

an active region, including a body, formed on a surface of the semiconductor substrate;

pillars formed on the body;

a supporter buried the active region; and

buried bit lines formed in the body and including fully silicided metal silicide,

wherein the supporter is formed between adjacent pillars and between adjacent buried bit lines.

2. The semiconductor device of claim 1 , further comprising:

a gate electrode for a vertical channel transistor formed on a sidewall of each of the pillars; and

a capacitor connected to each of the pillars.

3. The semiconductor device of claim 1 , wherein the supporter includes an insulation material.

4. The semiconductor device of claim 1 , wherein the supporter is formed in a bulb-type trench formed in the active region.

5. The semiconductor device of claim 1 , wherein a portion of the supporter extends between the body and the semiconductor substrate.

6. The semiconductor device of claim 1 , further comprising:

a punch-through prevention insulation layer formed between the semiconductor substrate and the body,

where a lower portion of each of the buried bit lines contacts the punch-through prevention insulation layer.

7. The semiconductor device of claim 1 ,

wherein the body is divided by a trench that bisects the active region, and

wherein the semiconductor device further comprises an insulation layer buried in the trench.

Priority Claims (1)
KR 10-2012-0094460 · Aug 28, 2012 · national
Continuity (2)
Division 13720109 · Dec 19, 2012
Related Publication 20150091070A1 · Apr 2, 2015