Non-local error detection in processor systems

1. A computer hardware device to delocalize an error checking on a data in a pipelined processor from the data checked the computer hardware device comprising:

a plurality of components, the plurality of components comprising:

a first group of components, included in a plurality of components, generates a first check-data at a first location on a first data at the first location;

a second group of components, included in the plurality of components, transfers the first data from the first location to a second location;

a third group of components, included in the plurality of components, transfers the first check-data from the first location to the second location;

a fourth group of components, included in the plurality of components, generates a second check-data on the first data at the second location;

a fifth group of components, included in the plurality of components, compares the first check-data with the second check-data at the second location;

a sixth group of components, included in the plurality of components, generates a second data from the first data at the second location;

a seventh group of components, included in the plurality of components, generates a third check-data on the second data at the second location;

an eighth group of components, included in the plurality of components, transfers the second data to a third location;

a ninth group of components, included in the plurality of components, transfers the third check-data from the second location to a fourth location wherein the transfer of the third check-data from the second location to the fourth location takes one or more cycles;

a tenth group of components, included in the plurality of components, generates a fourth check-data on the second data at the third location;

an eleventh group of components, included in the plurality of components, transfers the fourth check-data from the third location to the fourth location wherein a the transfer of the fourth check-data from the third location to the fourth location takes one or more cycles; and

a twelfth group of components, included in the plurality of components, compares the fourth check-data with the third check-data at the fourth location.

2. The computer hardware device of claim 1 , wherein the first location and the third location are data registers in a register file in a pipelined processor.

3. The computer hardware device of claim 2 , wherein the second location is an execution unit in a pipelined processor.

4. The computer hardware device of claim 1 , wherein the check-data is parity data.

5. The computer hardware device of claim 1 , wherein the check-data is ECC data.

6. The computer hardware device of claim 1 , wherein the fourth location is an ECC register file containing ECC check-data data.

7. The computer hardware device of claim 1 , wherein a data transfer from the third location to the fourth location takes one or more clock cycles.

8. A computer program product for delocalizing an error checking on a data in a pipelined processor from the data checked, the computer program product comprising:

one or more computer readable storage media and program instructions stored on the one or more computer readable storage media, the program instructions comprising:

program instructions to generate a first check-data at a first location on a first data at the first location;

program instructions to transfer the first data from the first location to a second location;

program instructions to transfer the first check-data from the first location to the second location;

program instructions to generate a second check-data on the first data at the second location;

program instructions to compare the first check-data with the second check-data at the second location;

program instructions to generate a second data from the first data at the second location;

program instructions to generate a third check-data on the second data at the second location;

program instructions to transfer the second data to a third location;

program instructions to transfer the third check-data from the second location to a fourth location wherein the transfer of the third check-data from the second location to the fourth location takes one or more cycles;

program instructions to generate a fourth check-data on the second data at the third location;

program instructions to transfer the fourth check-data from the third location to the fourth location wherein a the transfer of the fourth check-data from the third location to the fourth location takes one or more cycles; and

program instructions to compare the fourth check-data with the third check-data at the fourth location.

9. The computer program product of claim 8 , wherein the first location and the third location are data registers in a register file in a pipelined processor.

10. The computer program product of claim 9 , wherein the second location is an execution unit in a pipelined processor.

11. The computer program product of claim 8 , wherein the check-data is parity data.

12. The computer program product of claim 8 , wherein the check-data is ECC data.

13. The computer program product of claim 8 , wherein the fourth location is an ECC register file containing ECC check-data data.

14. A computer system for delocalizing an error checking on a data in a pipelined processor from the data checked, the computer system comprising:

one or more computer processors;

one or more computer readable storage medium;

program instructions stored on the computer readable storage medium for execution by at least one of the one or more processors, the program instructions comprising:

program instructions to generate a first check-data at a first location on a first data at the first location;

program instructions to transfer the first data from the first location to a second location;

program instructions to transfer the first check-data from the first location to the second location;

program instructions to generate a second check-data on the first data at the second location;

program instructions to compare the first check-data with the second check-data at the second location;

program instructions to generate a second data from the first data at the second location;

program instructions to generate a third check-data on the second data at the second location;

program instructions to transfer the second data to a third location;

program instructions to transfer the third check-data from the second location to a fourth location wherein the transfer of the third check-data from the second location to the fourth location takes one or more cycles;

program instructions to generate a fourth check-data on the second data at the third location;

program instructions to transfer the fourth check-data from the third location to the fourth location wherein a the transfer of the fourth check-data from the third location to the fourth location takes one or more cycles; and

program instructions to compare the fourth check-data with the third check-data at the fourth location.

15. The computer system of claim 14 , wherein the first location and the third location are data registers in a register file in a pipelined processor.

16. The computer system of claim 15 , wherein the second location is an execution unit in a pipelined processor.

17. The computer system of claim 14 , wherein the check-data is parity data.

18. The computer system of claim 14 , wherein the check-data is ECC data.

19. The computer system of claim 14 , wherein the fourth location is an ECC register file containing ECC check-data data.

20. The computer system of claim 14 , wherein a data transfer from the third location to the fourth location takes one or more clock cycles, and wherein a match between the fourth check-data and the third check-data indicates that no error has occurred.