High-speed voltage level shifter circuit
A level shifter includes a latch having first and second branches, first and second outputs, first and second control switches in series between the respective branches and outputs, and a controller receiving first and second output signals and outputting first and second control signals to the first and second control switches for controlling activation thereof. In an initial state, the first output signal is in the first state, the first control switch is activated, the second output signal is in the second state, and the second control switch is deactivated. In a final state, the first output signal is in the second state, the first control switch is deactivated, the second output signal is in the first state, and the second control switch is activated. The controller changes the first and second control signals only after the first and second output signals reach the respective second and first states.
1. A level shifter, comprising:
a latch supplied at a first voltage and having first and second branches;
a first output connected to the first branch and outputting a first output signal variable between a first state and a second state, and a second output connected to the second branch and outputting a second output signal variable between the first state and the second state;
a first control switch element connected in series between the first branch and the first output, and a second control switch element connected in series between the second branch and the second output;
a first switch element connected in series between the first output and a second voltage different from the first voltage, and a second switch element connected in series between the second output and the second voltage;
a controller receiving the first and second output signals and outputting a first control signal to the first control switch element for controlling activation thereof, and a second control signal to the second control switch element for controlling activation thereof;
a first boost switch element connected in series between a first input signal to the first switch element and the second output, and a second boost switch element connected in series between a second input signal to the second switch element and the first output,
wherein in an initial state of the level shifter, the first output signal is in the first state, the first control switch element is activated, the second output signal is in the second state, and the second control switch element is deactivated,
in a final state of the level shifter, the first output signal is in the second state, the first control switch element is deactivated, the second output signal is in the first state, and the second control switch element is activated, and
wherein the controller is configured to change the first and second control signals to deactivate the first control switch element and activate the second control switch element only after the first and second output signals reach the second and first states, respectively.
2. The level shifter of claim 1 , wherein the first and second switch elements are transistors, the first switch element having a gate connected to the first input signal and the second switch element having a gate connected to the second input signal.
3. The level shifter of claim 1 , wherein the first boost switch element receives a first boost signal for controlling activation thereof, and the second boost switch element receives a second boost signal for controlling activation thereof.
4. The level shifter of claim 3 , wherein the first boost signal is a delayed version of the first output signal and the second boost signal is a delayed version of the second output signal.
5. The level shifter of claim 4 , further comprising a buffer receiving the first and second outputs and outputting the first and second boost signals.
6. The level shifter of claim 1 , wherein the controller includes a first transistor pair and a second transistor pair, each transistor pair having a top transistor and a bottom transistor connected in series between the first voltage and the second voltage, the first control signal being output from a node between the top and bottom transistors of the first transistor pair, and the second control signal being output from a node between the top and bottom transistors of the second transistor pair.
7. The level shifter of claim 6 , wherein a gate of the bottom transistor of the first transistor pair is connected to the second output and a gate of the bottom transistor of the second transistor pair is connected to the first output.
8. The level shifter of claim 7 , wherein a gate of the top transistor of the first transistor pair receives a delayed and inverted version of the first output signal, and a gate of the top transistor of the second transistor pair receives a delayed and inverted version of the second output signal.
9. A level shifter circuit, comprising:
a latch supplied at a first voltage and having first and second branches;
a first output connected to the first branch and outputting a first output signal variable between a first state and a second state, and a second output connected to the second branch and outputting a second output signal variable between the first state and the second state;
a first control switch element connected in series between the first branch and the first output, and a second control switch element connected in series between the second branch and the second output;
a first switch element connected in series between the first output and a second voltage different from the first voltage, and a second switch element connected in series between the second output and the second voltage; and
a controller receiving the first and second output signals and outputting a first control signal to the first control switch element for controlling activation thereof, and a second control signal to the second control switch element for controlling activation thereof,
wherein in an initial state of the level shifter, the first output signal is in the first state, the first control switch element is activated, the second output signal is in the second state, and the second control switch element is deactivated,
in a final state of the level shifter, the first output signal is in the second state, the first control switch element is deactivated, the second output signal is in the first state, and the second control switch element is activated, and
wherein the controller is configured to change the first and second control signals to deactivate the first control switch element and activate the second control switch element only after the first and second output signals reach the second and first states, respectively, and
wherein the controller includes a NOR latch comprising a first NOR gate receiving the first output signal and the first control signal as inputs and outputting the second control signal, and a second NOR gate receiving the second output signal and the second control signal as inputs and outputting the first control signal.