Through substrate via with diffused conductive component
A front-end-of-line through-substrate via is provided for application in certain semiconductor device fabrication, including microelectromechanical (MEMS) devices. The through-substrate via (TSV) has a conductive element formed from the cylindrical core of a ring-shaped isolating etch trench. The conductivity of the core is provided by in-diffusion of dopants from a highly-doped layer deposited along sidewalls of the core within the etched trench. The highly-doped layer used as the diffusion source can be either conductive or insulating, depending upon the application. The highly-doped diffusion source layer can be retained after diffusion to further contribute to the conductivity of the TSV, to help fill or seal the via, or can be partially or completely removed. Embodiments provide for the drive in-diffusion process to use a same heating step as that used for thermal oxidation to fill or seal the via trench. Other embodiments can provide for diffusion elements from a gaseous source.
1. A method for manufacturing a semiconductor device having a through substrate via, the method comprising:
etching an annular trench in a first major surface of a low-conductivity crystalline silicon substrate to form a cylindrical core surrounded by the annular trench;
diffusing a dopant into the cylindrical core;
forming a thermal oxide layer to fill the annular trench after said diffusing the dopant;
exposing a conductive region in contact with the cylindrical core on the first major surface of the substrate after said diffusing the dopant and said forming the thermal oxide layer; and
exposing a conductive region in contact with the cylindrical core on a second major surface of the substrate after said diffusing the dopant and said forming the thermal oxide layer.
2. The method of claim 1 wherein said diffusing the dopant into the cylindrical core further comprises:
depositing a source layer comprising a high concentration of dopant on the substrate and annular trench walls; and
thermally diffusing the dopant during a first heating process associated with said forming the thermal oxide layer.
3. The method of claim 2 wherein said diffusing the dopant into the cylindrical core further comprises:
thermally diffusing the dopant during a second heating process preceding the first heating process.
4. The method of claim 3 wherein said second heating process comprises:
exposing the semiconductor device to a nitrogen gas; and
heating the semiconductor device to about 1150 C for up to four hours.
5. The method of claim 2 wherein the source layer comprises:
a polysilicon layer doped with an n-type dopant.
6. The method of claim 5 wherein the thermal oxide layer is formed on the polysilicon layer.
7. The method of claim 1 wherein said diffusing the dopant into the cylindrical core comprises:
exposing the semiconductor device to a gaseous dopant source; and
heating the semiconductor device to a temperature sufficient to drive in the gaseous dopant into the cylindrical core.
8. The method of claim 7 wherein the thermal oxide layer is formed on the crystalline core.
9. The method of claim 1 wherein said etching the annular trench comprises:
forming a mask layer on the first major surface of the substrate;
exposing an annular region of the first major surface of the substrate through the mask layer; and
performing a deep reactive ion etch to form the annular trench.
10. The method of claim 1 wherein said exposing the conductive region in contact with the cylindrical core on the first major surface of the substrate comprises:
polishing the first major surface to remove one or more of the thermal oxide layer, a source layer comprising a high concentration of dopant, and a mask layer.
11. The method of claim 1 further comprising:
forming a conductive contact electrically coupled to the conductive region in contact with the cylindrical core on the first major surface of the substrate.
12. The method of claim 1 wherein said exposing the conductive region in contact with the cylindrical core on the second major surface of the substrate comprises:
performing a backgrind operation to expose a portion of the doped cylindrical core and to remove the thermal oxide layer in the bottom of the annular trench.
13. The method of claim 1 further comprising:
forming a conductive contact electrically coupled to the conductive region in contact with the cylindrical core on the second major surface of the substrate.
14. The method of claim 13 wherein said forming the conductive contact comprises:
forming a dielectric layer on the second major surface;
etching an opening in the dielectric layer to expose the conductive region in contact with the cylindrical core on the second major surface of the substrate; and
forming a conductive layer in contact with the conductive region in contact with the cylindrical core on the second major surface of the substrate.
15. The method of claim 1 further comprising:
etching an outer annular trench in the first major surface of the low-conductivity crystalline silicon substrate to form an annular crystalline silicon region between the annular trench and the outer annular trench, wherein the outer annular trench has a same center point as the annular trench;
diffusing the dopant into the annular crystalline silicon region at the same time as diffusing the dopant into the cylindrical core;
forming the thermal oxide layer further comprises filling the outer annular trench in the same step as said forming the thermal oxide layer to fill the annular trench;
exposing a conductive region in contact with the doped annular crystalline silicon region on the first major surface of the substrate after said diffusing the dopant and said forming the thermal oxide layer; and
exposing a conductive region in contact with the doped annular crystalline silicon region on the second major surface of the substrate after said diffusing the dopant and said forming the thermal oxide layer.