Controlling a test run on a device under test without controlling the test equipment testing the device under test
View Patent ↗A test controller controlled by a design entity sends at least one closed type command of a closed loop architecture test flow to an arbiter of a vendor test platform controlled by a vendor entity, wherein the test controller controls nondeterministic testing on a protected integrated circuit (IC) integrated into an electronic assembly, as performed by test equipment hardware within the vendor test platform, without the design entity disclosing an underlying design of the protected IC to the vendor entity. In response to the test controller receiving at least one response of the at least one closed type command, from the arbiter interface passing the at least one closed type command directly through the test equipment hardware to the protected IC, determining, by the test controller, based on the at least one response, a next at least one closed type command of the closed loop architecture test flow to send to the arbiter.
1. A system for testing a device under test, comprising:
a processor, coupled with a memory, and configured to perform the actions of:
sending, by a test controller controlled by a design entity, at least one closed command of a closed loop architecture test flow, to an arbiter of a vendor test platform controlled by a vendor entity, wherein the test controller controls testing of the closed loop architecture test flow on a protected integrated circuit (IC) integrated into an electronic assembly, as performed by test equipment hardware within the vendor test platform, wherein an input and output of the closed loop architecture test flow are nondeterministic, wherein the at least one closed command does not disclose an underlying design of the protected IC to the vendor entity;
controlling, by the design entity, the closed loop architecture test flow for testing the protected IC integrated into the electronic assembly under test, such that the design entity controls running the at least one closed command sent by the closed loop architecture test flow, on the test equipment hardware, without disclosing the underlying design of the protected IC to the vendor entity, wherein the design entity discloses an arbiter specification to the vendor entity comprising an instruction for passing the at least one closed command to a secondary communication interface of the protected IC without interpretation, wherein the design entity is not required to specify the closed loop architecture test flow for controlling a specific environment of the test equipment hardware;
in response to the test controller receiving at least one response to the at least one closed command, from the arbiter passing the at least one closed command directly through the test equipment hardware to the protected IC, determining, by the test controller, based on a result of the testing of the at least one closed command in the at least one response, a next at least one closed command of the closed loop architecture test flow to send to the arbiter; and
sending, by the test controller, the next at least one closed command to the arbiter.
2. The system according to claim 1 , wherein the processor is further configured to perform the actions of:
sending, by the test controller controlled by the design entity, the at least one closed command comprising at least one of a read command and a write command.
3. The system according to claim 2 , wherein the processor is further configured to perform the actions of:
sending, by the test controller controlled by the design entity, the at least one closed command comprising the at least one of the read command and the write command in a format that is translatable by the arbiter into a command passed through a hardware abstraction layer for controlling a hardware layer of the protected IC.
4. The system according to claim 1 , wherein the processor is further configured to perform the actions of:
controlling, by the design entity, sending the at least one closed command in a format specified in the arbiter specification to be received by the arbiter and automatically passed through the test equipment hardware to the secondary communication interface comprising a Joint Test Action Group (JTAG) interface of the controlled IC without analysis by the arbiter of contents of the at least one closed command.
5. The system according to claim 1 , wherein the processor is further configured to perform the actions of:
controlling, by the design entity, sending the at least one closed command to the arbiter for the arbiter to automatically pass the at least one closed command to the second communication interface, wherein the protected IC comprises a plurality of first pins and a plurality of second pins, wherein when the protected IC is integrated into the electronic assembly, the first pins are hidden within the electronic assembly and the second pins are accessible as the secondary communication interface.
6. The system according to claim 1 , wherein the processor is further configured to perform the actions of:
sending, by the test controller, at least one open type command of a closed loop architecture test flow specifying a function, to the arbiter, wherein the arbiter is specified to analyze the open type command to determine the function specified in the at least one open type command and to control a signal on the electronic assembly for controlling the function, wherein the at least one open type command specifying the function is generic for controlling operation independent of a vendor test equipment hardware specification of the vendor test platform.
7. A computer program product for testing a device under test, the computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:
send, by a test controller controlled by a design entity, at least one closed command of a closed loop architecture test flow, to an arbiter of a vendor test platform controlled by a vendor entity, wherein the test controller controls testing of the closed loop architecture test flow on a protected integrated circuit (IC) integrated into an electronic assembly, as performed by test equipment hardware within the vendor test platform, wherein an input and output of the closed loop architecture test flow are nondeterministic, wherein the at least one closed command does not disclose an underlying design of the protected IC to the vendor entity;
control, by the design entity, the closed loop architecture test flow for testing the protected IC integrated into the electronic assembly under test, such that the design entity controls running the at least one closed command sent by the closed loop architecture test flow, on the test equipment hardware, without disclosing the underlying design of the protected IC to the vendor entity, wherein the design entity discloses an arbiter specification to the vendor entity comprising an instruction for passing the at least one closed command to a secondary communication interface of the protected IC without interpretation, wherein the design entity is not required to specify the closed loop architecture test flow for controlling a specific environment of the test equipment hardware;
in response to the test controller receiving at least one response to the at least one closed command, from the arbiter passing the at least one closed command directly through the test equipment hardware to the protected IC, determine, by the test controller, based on a result of the testing of the at least one closed command in the at least one response, a next at least one closedcommand of the closed loop architecture test flow to send to the arbiter; and
send, by the test controller, the next at least one closed command to the arbiter.
8. The computer program product according to claim 7 , further comprising the program instructions executable by a processor to cause the processor to:
send, by the test controller controlled by the design entity, the at least one closed command comprising at least one of a read command and a write command.
9. The computer program product according to claim 7 , further comprising the program instructions executable by a processor to cause the processor to:
control, by the design entity, sending the at least one closed command in a format specified in the arbiter specification to be received by the arbiter and automatically passed through the test equipment hardware to the secondary communication interface comprising a Joint Test Action Group (JTAG) interface of the controlled IC without analysis by the arbiter of contents of the at least one closed command.
10. The computer program product according to claim 7 , further comprising the program instructions executable by a processor to cause the processor to:
control, by the design entity, sending the at least one closed command to the arbiter for the arbiter to automatically pass the at least one closed command to the second communication interface, wherein the protected IC comprises a plurality of first pins and a plurality of second pins, wherein when the protected IC is integrated into the electronic assembly, the first pins are hidden within the electronic assembly and the second pins are accessible as the secondary communication interface.
11. The computer program product according to claim 7 , further comprising the program instructions executable by a processor to cause the processor to:
sending, by the test controller, at least one open type command of a closed loop architecture test flow specifying a function, to the arbiter, wherein the arbiter is specified to analyze the open type command to determine the function specified in the at least one open type command and to control a signal on the electronic assembly for controlling the function, wherein the at least one open type command specifying the function is generic for controlling operation independent of a vendor test equipment hardware specification of the vendor test platform.