Electrostatic discharge protection circuitry
Various implementations described herein are directed to an integrated circuit for electrostatic discharge (ESD) protection. The integrated circuit may include a detection stage having a resistor and a first capacitor cascaded with a second capacitor. The resistor and the first capacitor are arranged to define a triggering node configured to provide a triggering signal. The first capacitor and the second capacitor are arranged to define a reference node configured to provide a reference signal. The integrated circuit may include a first ESD clamping stage having a first transistor configured to provide a supply voltage to a first clamping transistor based on the triggering signal. The integrated circuit may include a second ESD clamping stage having a second transistor configured to receive the supply voltage from the first transistor and provide the supply voltage to a second clamping transistor based on the reference signal.
1. An integrated circuit, comprising:
a resistor-capacitor (RC) detection stage having a resistor and a first capacitor cascaded with a second capacitor, the resistor and the first capacitor arranged to define a triggering node that provides a RC triggering signal, the first capacitor and the second capacitor arranged to define a reference node that provides a reference signal;
a first electrostatic discharge (ESD) clamping stage having a first transistor configured to provide a supply voltage to a first clamping field effect transistor (FET) based on the RC triggering signal from the triggering node;
a second ESD clamping stage having a second transistor configured to receive the supply voltage from the first transistor and provide the supply voltage to a second clamping FET based on the reference signal from the reference node; and
a top-gate node defined between the first transistor and the second transistor, wherein the first transistor is configured to provide the supply voltage to the first clamping FET via the top-gate node, and wherein the second transistor is configured to receive the supply voltage from the first transistor via the top-gate node.
2. The integrated circuit of claim 1 , wherein:
each of the first and second transistors comprises a p-type metal-oxide-semiconductor (PMOS) transistor.
3. The integrated circuit of claim 1 , wherein:
each of the first and second clamping FETs comprises a n-type metal-oxide-semiconductor (NMOS) FET.
4. An integrated circuit, comprising:
a resistor-capacitor (RC) detection stage having a resistor and a first capacitor cascaded with a second capacitor, the resistor and the first capacitor arranged to define a triggering node that provides a RC triggering signal, the first capacitor and the second capacitor arranged to define a reference node that provides a reference signal;
a first electrostatic discharge (ESD) clamping stage having a first transistor configured to provide a supply voltage to a first clamping field effect transistor (FET) based on the RC triggering signal from the triggering node; and
a second ESD clamping stage having a second transistor configured to receive the supply voltage from the first transistor and provide the supply voltage to a second clamping FET based on the reference signal from the reference node, wherein:
the second ESD clamping stage comprises a third transistor, under non-ESD condition, the third transistor is configured to provide a ground voltage to a bottom-gate node based on the reference signal from the reference node; and
under ESD condition, the third transistor remains in a high impedance state.
5. The integrated circuit of claim 4 , further comprising:
a bottom-gate node defined between the second transistor and the third transistor, wherein the second transistor is configured to provide the supply voltage to the second clamping FET via the bottom-gate node.
6. The integrated circuit of claim 4 , wherein:
the third transistor comprises a n-type metal-oxide-semiconductor (NMOS) transistor.
7. An integrated circuit, comprising:
a resistor-capacitor (RC) detection stage having a resistor and a first capacitor cascaded with a second capacitor, the resistor and the first capacitor arranged to define a triggering node that provides a RC triggering signal, the first capacitor and the second capacitor arranged to define a reference node that provides a reference signal;
a first electrostatic discharge (ESD) clamping stage having a first transistor configured to provide a supply voltage to a first clamping field effect transistor (FET) based on the RC triggering signal from the triggering node;
a second ESD clamping stage having a second transistor configured to receive the supply voltage from the first transistor and provide the supply voltage to a second clamping FET based on the reference signal from the reference node; and
a third capacitor interposed between a gate of the second clamping FET and a gate of the first clamping FET, wherein the third capacitor is configured to receive the supply voltage from the first clamping FET at a top-gate node to the second clamping FET at a bottom-gate node by capacitive coupling in addition to a signal coming from a second transistor in the first ESD clamping stage.
8. The integrated circuit of claim 7 , wherein:
the third capacitor comprises a p-type metal-oxide-semiconductor (PMOS) transistor interconnected to function as a capacitor.
9. The integrated circuit of claim 4 , further comprising:
a fourth transistor configured to receive the supply voltage from the first transistor and add the supply voltage to the reference signal based on the RC triggering signal from the triggering node.
10. The integrated circuit of claim 9 , wherein:
the fourth transistor comprises a n-type metal-oxide-semiconductor (NMOS) transistor.
11. An integrated circuit, comprising:
a resistor-capacitor (RC) detection stage having a resistor and a first capacitor cascaded with a second capacitor, the resistor and the first capacitor arranged to define a triggering node that provides a RC triggering signal, the first capacitor and the second capacitor arranged to define a reference node that provides a reference signal;
a first electrostatic discharge (ESD) clamping stage having a first transistor configured to provide a supply voltage to a first clamping field effect transistor (FET) based on the RC triggering signal from the triggering node; and
a second ESD clamping stage having a second transistor configured to receive the supply voltage from the first transistor and provide the supply voltage to a second clamping FET based on the reference signal from the reference node, wherein:
the supply voltage provides a first power supply voltage, the reference signal provides a second power supply voltage less than the first power supply voltage, each of the first and second ESD clamping stages utilize circuit components configured for operating with the first and second power supply voltages, and none of the component's gate-to-source or gate-to-drain voltages exceed the second power supply voltage.
12. An integrated circuit, comprising:
a resistor-capacitor (RC) detection stage having a resistor and a first capacitor cascaded with a second capacitor, the resistor and the first capacitor arranged to define a triggering node that provides a RC triggering signal, the first capacitor and the second capacitor arranged to define a reference node that provides a reference signal;
a first electrostatic discharge (ESD) clamping stage having a first transistor configured to provide a supply voltage to a first clamping field effect transistor (FET) based on the RC triggering signal from the triggering node; and
a second ESD clamping stage having a second transistor configured to receive the supply voltage from the first transistor and provide the supply voltage to a second clamping FET based on the reference signal from the reference node, wherein:
the supply voltage comprises a high voltage (HV) power supply having an upper boundary voltage of 3.3V, the reference signal comprises a low voltage (LV) power supply having an upper boundary voltage of 1.8V, and each of the first and second ESD clamping stages utilize LV circuit components configured for operating with an upper boundary voltage of 1.8V.
13. An integrated circuit, comprising:
a resistor-capacitor (RC) detection stage having a resistor and a first capacitor cascaded with a second capacitor, the resistor and the first capacitor arranged to define a triggering node that provides a RC triggering signal, the first capacitor and the second capacitor arranged to define a reference node that provides a reference signal;
a first electrostatic discharge (ESD) clamping stage having a first transistor configured to provide a supply voltage to a first clamping field effect transistor (FET) based on the RC triggering signal from the triggering node; and
a second ESD clamping stage having a second transistor configured to receive the supply voltage from the first transistor and provide the supply voltage to a second clamping FET based on the reference signal from the reference node, wherein:
the supply voltage comprises a medium voltage (MV) power supply having an upper boundary voltage of 2.5V, the reference signal comprises a low voltage (LV) power supply having an upper boundary voltage of 1.8V, and each of the first and second ESD clamping stages utilize LV circuit components configured for operating with having an upper boundary voltage of 1.8V.
14. An electrostatic discharge (ESD) protection circuit, comprising:
a detection stage configured to provide a supply voltage to a top-gate node based on a resistor-capacitor (RC) triggering voltage and configured to provide the supply voltage to a bottom-gate node via the top-gate node based on a reference voltage;
a clamping stage configured to provide a first ESD clamp in response to receiving the supply voltage from the top-gate node and configured to provide a second ESD clamp in response to receiving the supply voltage from the bottom-gate node;
a coupling capacitor interposed between the bottom-gate node and the top-gate node, the coupling capacitor being configured to receive the supply voltage from the top-gate node to the bottom-gate node; and
a regulating transistor configured to receive the supply voltage from the top-gate node and add the supply voltage to the reference voltage based on the RC triggering voltage.
15. An electrostatic discharge (ESD) protection circuit, comprising:
a detection stage configured to provide a supply voltage to a top-gate node based on a resistor-capacitor (RC) triggering voltage and configured to provide the supply voltage to a bottom-gate node via the top-gate node based on a reference voltage;
a clamping stage configured to provide a first ESD clamp in response to receiving the supply voltage from the top-gate node and configured to provide a second ESD clamp in response to receiving the supply voltage from the bottom-gate node; and
a coupling capacitor interposed between the bottom-gate node and the top-gate node, the coupling capacitor being configured to receive the supply voltage from the top-gate node to the bottom-gate node, wherein:
the detection stage includes a first stage including a resistor, a first capacitor, and a second capacitor, the resistor and the first capacitor being arranged to provide the RC triggering voltage, the first capacitor and the second capacitor being arranged to provide the reference voltage,
the detection stage includes a second stage comprising a first transistor configured to provide the supply voltage to the top-gate node based on the RC triggering voltage, a second transistor configured to receive the supply voltage from the top-gate node and provide the supply voltage to the bottom-gate node based on the reference voltage, and a third transistor configured to receive the supply voltage from the bottom-gate node based on the reference voltage, and
the clamping stage comprises a first clamping transistor as the first ESD clamp and a second clamping transistor as the second ESD clamp.
16. An electrostatic discharge (ESD) protection circuit, comprising:
a detection stage configured to provide a supply voltage to a top-gate node based on a resistor-capacitor (RC) triggering voltage and configured to provide the supply voltage to a bottom-gate node via the top-gate node based on a reference voltage;
a clamping stage configured to provide a first ESD clamp in response to receiving the supply voltage from the top-gate node and configured to provide a second ESD clamp in response to receiving the supply voltage from the bottom-gate node; and
a regulating transistor configured to receive the supply voltage from the top-gate node and add the supply voltage to the reference voltage based on the RC triggering voltage.
17. The ESD protection circuit of claim 16 , further comprising:
a second transistor configured to receive the supply voltage from the top-gate node and provide the supply voltage to the bottom-gate node based on the reference voltage; and
a coupling capacitor interposed between the bottom-gate node and the top-gate node, the coupling capacitor configured to receive the supply voltage from the top-gate node to the bottom-gate node along with an active second transistor path which adds supply voltage to bottom-gate node based on the reference voltage.
18. The ESD protection circuit of claim 16 , wherein:
the detection stage includes a first stage including a resistor, a first capacitor, and a second capacitor, the resistor and the first capacitor being arranged to provide the RC triggering voltage, the first capacitor and the second capacitor being arranged to provide the reference voltage,
the detection stage includes a second stage having a first transistor configured to provide the supply voltage to the top-gate node based on the RC triggering voltage, a second transistor configured to receive the supply voltage from the top-gate node and provide the supply voltage to the bottom-gate node based on the reference voltage, and a third transistor configured to receive the supply voltage from the bottom-gate node based on the reference voltage, and
the clamping stage comprises a first clamping transistor as the first ESD clamp and a second clamping transistor as the second ESD clamp.