IP Library › Granted Patent US 9,595,354
Granted Patent B2
US 9,595,354 · App. 14/570,219 · Granted Mar 14, 2017

Nonvolatile memory refresh

Inventors: Thomas Kern (Ascheim, DE); Karl Hofmann (Munich, DE); Michael Goessel (Mahlow, DE)
Assignee: Infineon Technologies AG
G11C29/76G06F11/106G06F11/1048G11C7/04G11C11/1673G11C13/0033G11C29/028G11C29/42G11C29/50016G11C29/52H03M13/3715G11C11/1653G11C11/1675
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Quick Facts
Patent No.
US 9,595,354
App. No.
14/570,219
Granted
Mar 14, 2017
Kind
B2
Abstract

A system and method of refreshing a nonvolatile memory having memory cells. The method includes identifying one or more of the memory cells that do not satisfy a data retention test; remapping the one or more identified memory cells from original memory addresses to spare memory addresses; and refreshing the identified memory cells.

Claims (40)

1. A method of refreshing a nonvolatile memory having memory cells, the method comprising:

identifying one or more of the memory cells that do not satisfy a data retention test;

remapping the one or more identified memory cells from original memory addresses to spare memory addresses;

refreshing the one or more identified memory cells; and

remapping the one or more identified memory cells from the spare addresses back to the original addresses after the nonvolatile memory ceases to be at a temperature that is greater than a predetermined temperature.

2. The method of claim 1 , wherein the spare addresses are located in a mapping table stored in a volatile memory.

3. The method of claim 1 , wherein the spare addresses are located in a mapping table stored in a nonvolatile memory.

4. The method of claim 1 , wherein the identifying and remapping steps are performed at startup.

5. The method of claim 1 , further comprising:

identifying, using an error-correcting code algorithm, one or more of the memory cells having an error; and

remapping the one or more memory cells identified as having an error from original addresses to spare memory addresses.

6. The method of claim 5 , wherein the refreshing step comprises:

reading data from the one or more identified memory cells;

correcting the read data the error-correcting algorithm; and

writing the corrected data to the one or more identified memory cells.

7. The method of claim 1 , wherein the identifying and remapping steps are performed repeatedly.

8. The method of claim 1 , wherein the identifying step comprises determining the one or more memory cells that have a write time that is less than a predetermined amount of time.

9. The method of claim 1 , wherein the identifying step comprises determining the one or more memory cells that have a read current that is less than a predetermined current value.

10. The method of claim 1 , wherein the identifying step comprises determining the one or more memory cells that have a write current that is less than a predetermined current value.

11. The method of claim 1 , wherein the identifying step comprises determining the one or more memory cells that have a resistance that is greater than a predetermined resistance value.

12. The method of claim 1 , wherein the identifying step comprises determining the one or more memory cells that have an energy barrier that is less than a predetermined energy value.

13. The method of claim 1 , wherein the nonvolatile memory is a spin-transfer torque magnetic random access memory.

14. The method of claim 1 , further comprising:

refreshing the one or more identified memory cells only.

15. The method of claim 1 , further comprising:

refreshing the one or more identified memory cells more frequently than non-identified memory cells.

16. A memory refresh system, comprising:

a nonvolatile memory having memory cells;

a memory having a mapping table; and

a controller configured to:

identify one or more of the memory cells that do not satisfy a data retention test;

remap the one or more identified memory cells from original memory addresses to spare memory addresses;

refresh the identified memory cells; and

remap the one or more identified memory cells from the spare addresses back to the original addresses after the nonvolatile memory ceases to be at a temperature that is greater than a predetermined temperature.

17. The memory refresh system of claim 16 , wherein the nonvolatile memory is a spin-transfer torque magnetic random access memory.

18. A computer program product embodied on a non-transitory computer-readable medium comprising program instructions configured such that when executed by processing circuitry cause the processing circuitry to implement a method of refreshing a nonvolatile memory having memory cells, the method comprising:

identifying one or more of the memory cells that do not satisfy a data retention test;

remapping the one or more identified memory cells from original memory addresses to spare memory addresses;

refreshing the one or more identified memory cells; and

remapping the one or more identified memory cells from the spare addresses back to the original addresses after the nonvolatile memory ceases to be at a temperature that is greater than a predetermined temperature.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE SECOND ASSIGNOR'S SURNAME PREVIOUSLY RECORDED AT REEL: 034507 FRAME: 0471. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 30, 2015
From: HOFMANN, KARL
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035334/0312 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2014
From: KERN, THOMAS; HOFFMAN, KARL; GOESSEL, MICHAEL
To: INFINEON TECHNOLOGIES AG
Reel/Frame 034507/0471 →
Continuity (1)
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