IP Library Granted Patent US 9,614,485
Granted Patent B2
US 9,614,485 · App. 14/571,734 · Granted Apr 4, 2017

Amplifier circuit

Inventor: Masaru Sato (Isehara, JP)
Assignee: FUJITSU LIMITED
H03F3/605H03F1/56H03F3/607H03F2200/222H03F2200/387H03F2200/451
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Quick Facts
Patent No.
US 9,614,485
App. No.
14/571,734
Granted
Apr 4, 2017
Kind
B2
Abstract

An amplifier circuit includes: plural transistors; plural first transmission lines respectively connected between input terminals of the plural transistors; plural second transmission lines respectively connected between output terminals of the plural transistors; an input node connected to the input terminal of a first stage transistor among the plural transistors; an output node connected to the output terminal of a final stage transistor among the plural transistors; and a capacitance connected to the output terminal of the first stage transistor via a third transmission line.

Claims (29)

1. An amplifier circuit comprising:

plural transistors;

plural first transmission lines respectively configured to be connected between input terminals of the plural transistors;

plural second transmission lines respectively configured to be connected between output terminals of the plural transistors;

an input node configured to be connected to the input terminal of a first stage transistor among the plural transistors;

an output node configured to be connected to the output terminal of a final stage transistor among the plural transistors; and

a capacitance configured to be connected to the output terminal of the first stage transistor via a third transmission line not passed through a terminating resistor,

wherein the third transmission line has a line length such that output signals of the plural transistors and a reflected wave become same phase.

2. The amplifier circuit according to claim 1 ,

wherein a line length of the third transmission line is 0.11 times or more and 0.18 times or less of a wavelength at a center frequency of a signal input to the input node.

3. The amplifier circuit according to claim 1 ,

wherein a reference terminal of each of the plural transistors is connected to a reference potential node, and

the capacitance is connected between the third transmission line and the reference potential node.

4. The amplifier circuit according to claim 1 ,

wherein the transistor is an n-channel field-effect transistor,

the input terminal of the transistor is a gate terminal of the n-channel field-effect transistor, and

the output terminal of the transistor is a drain terminal of the n-channel field-effect transistor.

5. The amplifier circuit according to claim 1 ,

wherein the transistor is a pnp bipolar transistor,

the input terminal of the transistor is a base terminal of the pnp bipolar transistor, and

the output terminal of the transistor is an emitter terminal of the pnp bipolar transistor.

6. The amplifier circuit according to claim 1 ,

wherein the capacitance is a variable capacitance.

7. The amplifier circuit according to claim 1 , further comprising:

a terminating resistor configured to be connected to the input terminal of the final stage transistor.

8. The amplifier circuit according to claim 1 , further comprising:

a bias power supply configured to be connected to the output terminal of the first stage transistor via the third transmission line.

9. The amplifier circuit according to claim 1 ,

wherein line widths of the plural second transmission lines become wider as they are near the output node.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2015
From: SATO, MASARU
To: FUJITSU LIMITED
Reel/Frame 034855/0856 →
Priority Claims (1)
JP 2014-044010 · Mar 6, 2014 · national
Continuity (1)
Related Publication 20150256129A1 · Sep 10, 2015