Contact for vertical memory with dopant diffusion stopper and associated fabrication method
A memory device and corresponding fabrication method prevent undesired diffusion of dopants from a silicon cap of a vertical NAND string to a channel film of the NAND string. Initially, a memory hole is provided in a stack of alternating control gate layers and dielectric layers. The memory hole is filled with annular films and a dielectric core filler. The dielectric core filler is etched back from a top of the memory hole to a topmost control gate layer, forming a void. A dopant stopper liner is deposited in the void before depositing n+ doped silicon which forms the silicon cap. The dopant stopper liner can be a conductive material such as metal or polysilicon doped with carbon. A conductive via is then formed above, and aligned with, the top of the silicon cap. A bit line may be formed over the conductive via.
1. A method for fabricating a contact in a memory device, comprising:
forming a vertically-extending memory hole in a stack, the stack comprising alternating control gate layers and dielectric layers;
providing a channel film in the vertically-extending memory hole, a central void in the vertically-extending memory hole is formed within the channel film;
providing a dielectric core filler in the central void;
forming a void in the vertically-extending memory hole, the forming the void comprises etching back the dielectric core filler to provide an etched back dielectric core filler;
providing a dopant stopper liner in the void, the dopant stopper liner is conductive and extends upward from a top surface of the etched back dielectric core filler to a top of the stack;
providing n+ doped silicon in the void, above the dopant stopper liner, the n+ doped silicon conforms to the dopant stopper liner;
providing a conductive via which extends above the stack, the conductive via has a bottom surface which rests on a top surface of the n+ doped silicon, wherein the channel film and the dielectric core filler extend to a top of the vertically-extending memory hole before the forming the void, and at least a portion of the channel film remains at the top of the stack after the etching back of the dielectric core filler; and
performing ion implantation which implants ions at a top of the n+ doped silicon and at a top of the at least the portion of the channel film.
2. The method of claim 1 , wherein:
the dielectric core filler is etched back to a height of a topmost control gate layer of the control gate layers in the stack, and the topmost control gate layer is a select gate layer.
3. The method of claim 1 , wherein:
the dopant stopper liner comprises metal.
4. The method of claim 1 , wherein:
the dopant stopper liner comprises polysilicon doped with carbon at a concentration of 10 21 to 10 22 atoms per cm 3 .
5. The method of claim 1 , wherein:
the n+ doped silicon is deposited as amorphous silicon.
6. The method of claim 1 , further comprising:
performing a heating step to activate the implanted ions in the n+ doped silicon and in the at least the portion of the channel film.
7. The method of claim 6 , wherein:
the performing the heating step comprises performing rapid thermal annealing at 900-1000 C for 10-30 seconds.
8. The method of claim 1 , wherein the providing the conductive via comprises:
providing an etch stop layer above the stack including above the top surface of the n+ doped silicon;
providing an oxide layer above the etch stop layer;
patterning the oxide layer and then the etch stop layer using different etch chemistries to form a pillar-shaped void above the vertically-extending memory hole; and
providing a conductive material in the pillar-shaped void above the vertically-extending memory hole.
9. The method of claim 1 , wherein:
the conductive via connects the n+ doped silicon to a metal bit line.