Integrated circuit assembly and method of making
View Patent ↗A first wafer is provided that includes an insulating layer, a first active layer, and a handle layer. The insulating layer has a first surface and a second surface. The first active layer contacts the first surface of the insulating layer. The handle layer contacts the second surface of the insulating layer. A second wafer is provided that includes a substrate and a second active layer. The substrate has a first surface and a second surface. The second active layer contacts the first surface of the substrate. The second wafer is bonded to the first wafer by physically connecting the first active layer to the second surface of the substrate. The handle layer is removed. A metal bond pad is formed on the second surface of the insulating layer. The metal bond pad is electrically connected to the first active layer.
1. A method comprising:
providing a first wafer including:
an insulating layer having a first surface and a second surface;
a first active layer contacting the first surface of the insulating layer;
a handle layer contacting the second surface of the insulating layer;
providing a second wafer including:
a substrate having a first surface and a second surface;
a second active layer contacting the first surface of the substrate;
bonding the second wafer to the first wafer by physically connecting the first active layer to the second surface of the substrate;
removing the handle layer; and
forming a metal bond pad on the second surface of the insulating layer;
wherein the metal bond pad is electrically connected to the first active layer.
2. The method of claim 1 further comprising forming a metal bond pad on the second active layer.
3. The method of claim 1 further comprising thinning the substrate before physically connecting the first active layer to the second surface of the substrate.
4. The method of claim 1 , wherein the substrate is a semiconductor wafer.
5. The method of claim 1 , wherein the first active layer comprises a complementary metal-oxide-semiconductor circuit.
6. The method of claim 1 , wherein the first active layer or the second active layer includes passive devices.
7. The method of claim 1 , further comprising:
singulating the bonded first and second wafers into individual integrated circuit chips.
8. The method of claim 1 , further comprising:
electrically connecting a printed circuit board to the first active layer and the second active layer.
9. The method of claim 8 , wherein the step of electrically connecting the printed circuit board to the first active layer and the second active layer comprises:
forming a second metal bond pad on the second active layer;
forming a solder bump on the first metal bond pad on the second surface of the insulating layer;
attaching the solder bump to a third metal bond pad on the printed circuit board; and
wire bonding the second metal bond pad on the second active layer to a fourth metal bond pad on the printed circuit board.
10. The method of claim 8 , wherein the step of electrically connecting the printed circuit board to the first active layer and the second active layer comprises:
forming a second metal bond pad on the second active layer;
forming a solder bump on the second metal bond pad on the second active layer;
attaching the solder bump to a third metal bond pad on the printed circuit board; and
wire bonding the first metal bond pad on the second surface of the insulating layer to a fourth metal bond pad on the printed circuit board.
11. The method of claim 1 , wherein the step of physically connecting the first active layer to the second surface of the substrate comprises fusion bonding of two surfaces.
12. The method of claim 1 , wherein the step of physically connecting the first active layer to the second surface of the substrate comprises:
applying an adhesive layer to the second surface of the substrate; and
contacting the first active layer to the adhesive layer.
13. The method of claim 1 , wherein the step of physically connecting the first active layer to the second surface of the substrate comprises aligning the substrate with the first active layer to an accuracy of no less than 5 microns.
14. The method of claim 1 , wherein the first wafer is a semiconductor-on-insulator.