Device having a shield plate dopant region and method of manufacturing same
A transistor includes a surface region, a gate, a source dopant region, a drain dopant region, a drift dopant region, a set of electrically conductive shield plates, and a shield plate dopant region. A sidewall of the gate aligns with a drain side boundary of the surface region. The drain dopant region is within the surface region on the drain side. The drift dopant region is within the surface region between the drain side boundary and the drain dopant region. The set of electrically conductive shield plates includes a first shield plate overlying the drift dopant region. The shield plate dopant region is within the drift dopant region and underlies the set of shield plates.
1. A transistor comprising:
a surface region;
a gate disposed on the surface region, the gate having a first sidewall and a second sidewall, wherein the first sidewall aligns with a source side boundary that defines a source side of the surface region, and the second sidewall aligns with a drain side boundary that defines a drain side of the surface region, wherein the source and drain side boundaries define lateral boundaries for a channel region within the surface region underlying the gate;
a drain dopant region disposed within the surface region on the drain side;
a drift dopant region disposed within the surface region between the drain side boundary and the drain dopant region;
a set of electrically conductive shield plates that includes at least a first shield plate overlying a portion of the drift dopant region; and
a shield plate dopant region disposed within the drift dopant region and underlying the set of shield plates.
2. The transistor of claim 1 , wherein the set of shield plates further comprises an electrically conductive second shield plate underlying the first shield plate, such that the first shield plate is a topmost shield plate, wherein the second shield plate overlies a second portion of the drift dopant region.
3. The transistor of claim 2 , wherein an end of the first shield plate is located further from the drain side boundary than an end of the second shield plate, and wherein an entirety of the shield plate dopant region is located between the drain side boundary and a boundary that aligns with the end of the first shield plate.
4. The transistor of claim 3 , wherein the shield plate dopant region only partially underlies the second shield plate.
5. The transistor of claim 1 , wherein the shield plate dopant region is disposed a gap distance away from the drain side boundary.
6. The transistor of claim 5 , wherein the gap distance is less than half a length of the drift dopant region.
7. The transistor of claim 1 , wherein the shield plate dopant region has a width within a range of 0.2 microns to 1.1 microns.
8. The transistor of claim 1 , wherein the shield plate dopant region comprises at least one of arsenic, phosphorous, or antimony dopant ions.
9. The transistor of claim 1 , wherein the shield plate dopant region comprises dopant ions having an opposite conductivity type as a conductivity type of the channel region, and a same conductivity type as a conductivity type of the drift dopant region.
10. The transistor of claim 1 , wherein the transistor is a laterally diffused metal-oxide semiconductor field-effect transistor.
11. The transistor of claim 1 , wherein at least one of the shield plates of the set of shield plates aligns with the second sidewall and overlies a top portion of the gate.
12. The transistor of claim 1 , wherein at least a portion of the shield plate dopant region extends into the channel region.
13. The transistor of claim 1 , wherein the set of shield plates comprises a plurality of shield plates, and the shield plate dopant region underlies only a subset of the set of shield plates.
14. A semiconductor device comprising:
semiconductor material having a surface region;
a gate dielectric overlying the surface region of the semiconductor material;
a gate electrode overlying the gate dielectric, the gate electrode having a first sidewall that aligns with a first gate region boundary and a second sidewall that aligns with a second gate region boundary;
a drift dopant region disposed within the surface region and extending from the second gate region boundary to an area beyond the second gate region boundary;
a set of electrically conductive shield plates overlying a portion of the drift dopant region; and
a shield plate dopant region disposed within the drift dopant region and underlying the set of shield plates.
15. The semiconductor device of claim 14 , wherein the semiconductor device is a field-effect transistor.
16. The semiconductor device of claim 14 , wherein the set of shield plates comprises a plurality of shield plates having a topmost shield plate, wherein an entirety of the shield plate dopant region is located between the second gate region boundary and a boundary aligned with an end of the topmost shield plate.
17. The semiconductor device of claim 14 , wherein the shield plate dopant region comprises dopant ions having a same conductivity type as dopant ions within the drift dopant region.
18. The semiconductor device of claim 14 , wherein the drift dopant region has a depth within a range of 0.6 micron to 4 microns.