Time domain ramp rate control for erase inhibit in flash memory
When performing an erase on a flash type non-volatile memory with a NAND type of structure, techniques are presented for inhibiting erase on selected word lines, select lines of programmable select transistors, or some combination of these. The voltage along the selected control lines are initially ramped up by the level on a corresponding input line, but then have their voltage raised to an erase inhibit level by capacitive coupling with the well structure. The level of these input signals are ramped up with the erase voltage applied to the well structure, but with a delay based upon the coupling ratio between the control line and the well.
1. A non-volatile memory circuit, comprising:
a string of a plurality of series connected programmable threshold transistors formed on a common channel structure;
a plurality of control lines along which control gates of the programmable threshold transistors are connected;
driver circuitry connectable to the control lines and to the channel structure;
a plurality of input lines connected to the driver circuitry;
a plurality of commonly controlled decoding transistors through which the driver circuitry is selectably connectable through the input lines to the control lines; and
decoder circuitry connectable to control gates of the decoding transistors, wherein each of the input lines is connected to a corresponding one of the control lines through a corresponding one of the decoding transistors,
wherein, when performing an erase operation on the string, the decoding circuitry applies a select voltage to the control gates of the commonly controlled decoding transistors and,
wherein, with the decoding transistors on, the driving circuitry:
applies an erase enable voltage to the input lines connected through corresponding ones of the decoding transistors to the control gates of programmable threshold transistors selected for erase,
applies a voltage that ramps up to an erase level to the channel structure, and
for a plurality of programmable threshold transistors selected to not be erased, applies an erase inhibit voltage to the input lines connected through corresponding ones of the decoding transistors, wherein after a delay the erase inhibit voltage ramps up with the voltage applied to the channel structure to a level sufficient to turn off the corresponding ones of the decoding transistors, where the amount of delay is one of a plurality of values dependent upon the location of the programmable threshold transistors within the string to which the erase inhibit voltage is applied.
2. The non-volatile memory circuit of claim 1 , wherein the programmable threshold transistors selected to not be erased includes select gate transistors of the string and the programmable threshold transistors selected for erase includes memory cells.
3. The non-volatile memory circuit of claim 1 , wherein the programmable threshold transistors selected to not be erased includes dummy memory cells and the programmable threshold transistors selected for erase includes memory cells used for the storing of user data.
4. The non-volatile memory circuit of claim 1 , wherein the programmable threshold transistors selected to be erased includes select gate transistors of the string and the programmable threshold transistors selected to not be erased includes memory cells.
5. The non-volatile memory circuit of claim 1 , wherein the programmable threshold transistors selected to be erased includes dummy memory cells and the programmable threshold transistors selected to not be erased includes memory cells used for the storing of user data.
6. The non-volatile memory circuit of claim 1 , wherein the programmable threshold transistors selected to be erased includes dummy memory cells and the programmable threshold transistors selected to be erased includes memory cells used for the storing of user data.
7. The non-volatile memory circuit of claim 1 , wherein the erase inhibit voltage ramps up to at least the select voltage applied to the control gates of the commonly controlled decoding transistors.
8. The non-volatile memory circuit of claim 1 , wherein the erase inhibit voltage ramps up to a level offset below the select voltage applied to the control gates of the commonly controlled decoding transistors, wherein the offset is related to a threshold voltage of the commonly controlled decoding transistors.
9. The non-volatile memory circuit of claim 1 , wherein the memory circuit is a monolithic two-dimensional semiconductor memory device where the programmable threshold transistors are arranged in single physical level above a silicon substrate and comprise a charge storage medium.
10. The non-volatile memory circuit of claim 9 , wherein channel structure is within the substrate.
11. The non-volatile memory circuit of claim 1 , wherein memory circuit is a monolithic three-dimensional semiconductor memory device where the programmable threshold transistors are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.
12. The non-volatile memory circuit of claim 11 , wherein the string is formed above a well structure and runs in a vertical direction relative to the substrate, and wherein the driving circuitry applies the voltage that ramps up to an erase level to the channel structure through the well structure.
13. The non-volatile memory circuit of claim 1 , wherein amount of delay of the programmable threshold transistors on a drain side of the string of a plurality of series connected programmable threshold transistors is greater than the amount of delay of the programmable threshold transistors on a source side of the string of a plurality of series connected programmable threshold transistors.
14. The non-volatile memory circuit of claim 1 , wherein the programmable threshold transistors selected to be erased includes select gate transistors of the string and the programmable threshold transistors selected to not be erased includes dummy memory cells.
15. The non-volatile memory circuit of claim 1 , wherein the programmable threshold transistors selected to be erased includes one or more first select gate transistors of the string and the programmable threshold transistors selected to not be erased includes one or more second select gate transistors.