IP Library › Granted Patent US 10,007,549
Granted Patent B2
US 10,007,549 · App. 14/581,772 · Granted Jun 26, 2018

Apparatus and method for a profiler for hardware transactional memory programs

Inventors: Justin E. Gottschlich (Santa Clara, CA); Gilles A. Pokam (Fremont, CA); Shiliang Hu (Los Altos, CA)
Assignee: Intel Corporation
G06F9/467G06F9/3004G06F9/30087G06F9/44563G06F12/084G06F12/0811G06F12/0813
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,007,549
App. No.
14/581,772
Granted
Jun 26, 2018
Kind
B2
Abstract

An apparatus and method are described for a hardware transactional memory (HTM) profiler. For example, one embodiment of an apparatus comprises a transactional debugger (TDB) recording module to record data related to the execution of transactional memory program code, including data related to the execution of branches and transactional events in the transactional memory program code; and a profiler to analyze portions of the recorded data using trace-based replay techniques to responsively generate profile data comprising transaction-level events and function-level conflict data usable to optimize the transactional memory program code.

Claims (28)

1. An apparatus comprising:

a transactional debugger (TDB) recording circuitry to record data related to the execution of transactional memory program code, including data related to the execution of branches and transactional events in the transactional memory program code;

a profiler circuitry to perform a plurality of tasks to analyze portions of the recorded data using trace-based replay techniques to responsively generate profile data comprising transaction-level events and function-level conflict data usable to optimize the transactional memory program code, wherein the plurality of tasks comprises:

analyzing the data related to the execution of branches and transactional events to generate the transaction-level events with function-level conflict data;

extracting the transaction-level events and cross-correlate the transaction-level events to disassembled binary information from the transactional memory program code, and

generating a result of the cross-correlation comprising an identified function which was executed when a transaction abort operation occurred, wherein when a transaction abort is detected for a transaction, the profiler circuitry is to perform a reverse lookup to identify a corresponding transaction begin event and, once identified, to capture a timestamp range of all possible branches taken during the transaction's execution, the profiler circuitry is further to compare instruction pointers (IPs) from the branches contained within the surrounding timestamp range against the disassembled binary information from the transactional memory program code to identify corresponding IPs in the disassembled binary information.

2. The apparatus as in claim 1 wherein the profiler circuitry is additionally to identify one or more functions that use those IPs, thereby allowing a user to see which one or more functions should be analyzed for performance optimizations.

3. The apparatus as in claim 1 further comprising:

data parsing circuitry to extract the portions of the recorded data related to the execution of transactional memory program code to be analyzed by the profiler circuitry.

4. The apparatus as in claim 3 wherein the data parsing circuitry is to extract shared memory and transactional event packet information recorded by the TDB recording circuitry.

5. The apparatus as in claim 4 wherein the transactional event packet information includes timestamp information indicating times associated with different transactional events.

6. The apparatus as in claim 5 wherein the universal timestamp information comprises transaction start timing data, transaction end timing data, and/or transaction abort timing data.

7. The apparatus as in claim 4 wherein the transactional event packet information further includes branch trace packet information comprising information about branches that are taken throughout the transactional memory program code.

8. A method comprising:

recording data related to the execution of transactional memory program code, including data related to the execution of branches and transactional events in the transactional memory program code;

analyzing portions of the recorded data using trace-based replay techniques to responsively generate profile data comprising transaction-level events and function-level conflict data usable to optimize the transactional memory program code, including analyzing the data related to the execution of branches and transactional events to generate the transaction-level events with function-level conflict data and extracting the transaction-level events and cross-correlate the transaction-level events to disassembled binary information from the transactional memory program code;

generating a result of the cross-correlation comprising an identified function which was executed when a transaction abort operation occurred;

performing a reverse lookup to identify a corresponding transaction begin event when a transaction abort is detected for a transaction;

once the corresponding transaction begin event is identified, capturing a timestamp range of all possible branches taken during the transaction's execution; and

comparing instruction pointers (IPs) from the branches contained within the surrounding timestamp range against the disassembled binary information from the transactional memory program code to identify corresponding IPs in the disassembled binary information.

9. The method as in claim 8 further comprising:

identifying one or more functions that use those IPs, thereby allowing a user to see which one or more functions should be analyzed for performance optimizations.

10. The method as in claim 8 , further comprising:

extracting the portions of the recorded data related to the execution of transactional memory program code to be analyzed by a profiler circuitry.

11. The method as in claim 10 , further comprising: extracting shared memory and transactional event packet information recorded by a TDB recording circuitry.

12. The method as in claim 11 wherein the transactional event packet information includes timestamp information indicating times associated with different transactional events.

13. The method as in claim 12 wherein the universal timestamp information comprises transaction start timing data, transaction end timing data, and/or transaction abort timing data.

14. The method as in claim 11 wherein the transactional event packet information further includes branch trace packet information comprising information about branches that are taken throughout the transactional memory program code.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 6, 2017
From: GOTTSCHLICH, JUSTIN E.; POKAM, GILLES A.; HU, SHILIANG
To: INTEL CORPORATION
Reel/Frame 041186/0286 →
Continuity (1)
Related Publication 20160179569A1 · Jun 23, 2016
Cited By (2)
US 12,632,254 US 12,724,614