Short channel effect suppression

1. A method of fabricating a semiconductor device, the method comprising:

forming a plurality of isolation features on a semiconductor substrate, thereby defining a first set of semiconductor features;

performing an etching process on the first set of semiconductor features such that larger semiconductor features are etched deeper than smaller semiconductor features;

after the etching process, epitaxially forming anti-punch-through features on surfaces of the exposed features of the first set of semiconductor features;

forming a semiconductor layer over the anti-punch-through features;

removing a portion of the isolation features to expose at least a portion of the anti-punch-through features; and

forming transistors on the semiconductor layer of each of the features of the first set of semiconductor features.

2. The method of claim 1 , wherein the anti-punch-through features comprise a higher doping concentration than the semiconductor layer.

3. The method of claim 1 , wherein forming the semiconductor layer comprises performing an epitaxial growth process to for the semiconductor layer.

4. The method of claim 1 , wherein the semiconductor layer comprises silicon germanium at a ratio of silicon to germanium within a range of about 1:0.1-0.9.

5. The method of claim 1 , wherein the semiconductor layer is doped with a p-type dopant.

6. The method of claim 1 , further comprising:

forming a second set of semiconductor features, the second set of features being separated by isolation features; and

forming anti-punch-through features below a top surface of the features of the second set of semiconductor features, each of the anti-punch-through features of the second set of semiconductor features being at substantially equal depths.

7. The method of claim 6 , wherein forming the anti-punch-through features of the second set of semiconductor features comprises one of: performing an implanting process, performing a diffusion process, and performing an epitaxial growth process.

8. The method of claim 1 , further comprising, performing an annealing process after forming the anti-punch-through features.

9. The method of claim 1 , wherein the anti-punch-through features comprise a p-type dopant.

10. The method of claim 1 , wherein the anti-punch-through features comprise a doping concentration within a range of 1×10 17 /cm 3 -1×10 18 /cm 3 and the semiconductor layer comprises a doping concentration within a range of 1×10 15 /cm 3 -1×10 16 /cm 3 .

11. A method comprising:

for an n-type region, forming a first set of fin structures, the fin structures of the first set varying in size;

forming n-type anti-punch-through features in the fin structures of the first set, the n-type anti-punch-through feature being at substantially a same depth for each of the fin structures of the first set;

for a p-type region, forming a second set of fin structures, the fin structures of the second set varying in size; and

after forming the second set of fin structures, epitaxially forming p-type anti-punch-through features in the fin structures of the second set, the p-type anti-punch-through features being at different depths for each of the fin structures of the second set;

forming isolation features between the second set of fin structures, a top surface of the isolation features being below at least a portion of the p-type anti-punch-through features.

12. The method of claim 11 , wherein forming the n-type anti-punch-through features comprises performing an ion implantation process to introduce dopants below a surface of the first set of fin structure.

13. The method of claim 11 , wherein forming the p-type anti-punch-through features comprises performing an ion implantation process at a surface of the second set of fin structures.

14. The method of claim 11 , further comprising, forming a silicon germanium layer on top of the p-type anti-punch-through features.

15. The method of claim 11 , wherein different depths of the p-type anti-punch-through features are based on a size of corresponding fin structures.

16. The method of claim 15 , wherein larger fin structures have deeper anti-punch-through features.

17. The method of claim 11 , further comprising:

forming n-type transistors on the first set of fin structures; and

forming p-type transistors on the second set of fin structures.

18. A semiconductor device comprising:

a p-type region comprising:

a first set of fin structures, the fin structures of the first set varying in size, the fin structures of the first set each comprising:

a bottommost portion;

a channel portion disposed above the bottommost portion and having an n-type dopant at a first concentration; and

an epitaxially grown anti-punch-through feature extending from the bottommost portion to the channel portion and having an n-type dopant throughout at a second concentration greater than the first concentration, wherein the anti-punch-through feature of a first fin structure of the first set extends to a different depth than the anti-punch-through feature of a second fin structure of the first set;

a plurality of p-type transistors formed on the fin structures of the first set, the p-type transistors having varying dimensions; and

a number of isolation features positioned such that a top surface of the isolation features is below a first portion of each of the anti-punch-through features and above a second portion of each of the anti-punch-through features.

19. The semiconductor device of claim 18 , further comprising:

an n-type region comprising:

a second set of fin structures, the fin structures of the second set varying in size, the fin structures of the second set comprising anti-punch-through features at substantially similar depths; and

a plurality of n-type transistors formed on the fin structures of the second set, the n-type transistors having varying channel lengths.

20. The semiconductor device of claim 19 , wherein a channel material for the n-type transistors comprises silicon and a channel material for the p-type devices comprises silicon germanium.