IP Library Granted Patent US 9,240,385
Granted Patent B2
US 9,240,385 · App. 14/583,984 · Granted Jan 19, 2016

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices

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Quick Facts
Patent No.
US 9,240,385
App. No.
14/583,984
Granted
Jan 19, 2016
Kind
B2
Abstract

Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.

Claims (53)

1. A method of forming a plurality of microelectronic devices on a semiconductor workpiece, the method comprising:

placing a plurality of first conductive balls on corresponding terminals of the semiconductor workpiece, individual conductive balls having a proximal portion proximate to the semiconductor workpiece and a distal portion opposite the proximal portion;

molding a protective layer on the semiconductor workpiece and on corresponding terminals with the protective layer covering only a portion of the individual first conductive balls, the protective layer having a first surface facing the semiconductor workpiece and a second surface opposite the first surface, wherein the distal portions of the individual first conductive balls project from the second surface of the protective layer;

reshaping the first conductive balls by heating to form the distal portions of the conductive balls generally flat without removing material from the conductive balls, such that a top surface of the plurality of conductive balls located opposite the corresponding terminals are reshaped to include a flat surface spaced apart from the protective layer, wherein a diameter of the flat distal portions of the individual first conductive balls is smaller than a corresponding aperture in the second surface of the protective layer; and

after reshaping the first conductive balls, coupling a first portion of a plurality of individual second conductive balls on the flat surface of corresponding first conductive balls with a second portion of the individual second conductive balls being exposed, wherein the second portion is opposite the first portion.

2. The method of claim 1 wherein:

the semiconductor workpiece comprises a plurality of dies and a redistribution structure on the dies, the redistribution structure including a plurality of terminals;

placing the first conductive balls on the workpiece comprises forming the first conductive balls on corresponding terminals of the redistribution structure;

forming the layer on the workpiece comprises molding a protective layer onto the workpiece;

coupling the detached second conductive balls comprises attaching the detached second conductive balls to the generally flat surfaces of the corresponding first conductive balls; and

the method further comprises (a) cutting the semiconductor workpiece to separate the individual dies after coupling the detached second conductive balls, and (b) attaching a separated die to a support member with the second conductive balls attached to corresponding pads on the support member.

3. The method of claim 1 wherein reshaping the first conductive balls comprises reconfiguring the first conductive balls without removing material from the layer.

4. The method of claim 1 wherein:

the semiconductor workpiece comprises a plurality of dies and a redistribution structure on the dies, the redistribution structure including a plurality of terminals; and

placing the first conductive balls on the workpiece comprises forming the first conductive balls on corresponding terminals of the redistribution structure.

5. The method of claim 1 wherein:

the semiconductor workpiece comprises a plurality of dies having an integrated circuit and a plurality of terminals operably coupled to the integrated circuit; and

placing the first conductive balls on the workpiece comprises forming the first conductive balls on corresponding terminals of the dies.

6. The method of claim 1 wherein:

the semiconductor workpiece comprises a plurality of dies having an integrated circuit and a plurality of terminals operably coupled to the integrated circuit;

placing the first conductive balls on the workpiece comprises forming the first conductive balls on the side of the workpiece with the first conductive balls electrically connected to corresponding terminals on the dies; and

the method further comprises cutting the workpiece to separate the dies after coupling the detached second conductive balls.

7. The method of claim 1 wherein:

forming the layer comprises constructing the layer with an end portion of the individual first conductive balls projecting a first distance from the layer; and

reshaping the first conductive balls comprises reconfiguring the first conductive balls with the end portion of the individual first conductive balls projecting a second distance from the layer, the second distance being less than the first distance.

8. A method of forming a plurality of microelectronic devices on a semiconductor workpiece having a plurality of microelectronic dies, the method comprising:

forming a plurality of first conductive balls on corresponding terminals of the semiconductor workpiece, individual conductive balls having a proximal portion proximate to the semiconductor workpiece and a distal portion opposite the proximal portion;

molding a layer onto the semiconductor workpiece with the layer covering only a portion of the individual first conductive balls, the layer having a first surface facing the semiconductor workpiece and a second surface opposite the first surface, wherein the distal portions of the individual first conductive balls project from the second surface of the layer;

reshaping the first conductive balls by heating to form the distal portions of the conductive balls generally flat without removing material from the conductive balls, such that a top surface of the plurality of conductive balls located opposite the corresponding terminals are reshaped to include a flat surface spaced apart from the protective layer, wherein a diameter of the flat distal portions of the individual first conductive balls is smaller than a corresponding aperture in the second surface of the layer; and

attaching a plurality of second conductive balls on the flat surface of corresponding first conductive balls.

9. The method of claim 8 wherein molding the layer comprises pressing the first conductive balls into a compressible member in a mold cavity with a distal end of the individual first conductive balls projecting from the layer.

10. The method of claim 8 , further comprising reconfiguring the first conductive balls after molding the layer.

11. The method of claim 8 wherein the workpiece comprises a first side having the terminals and a second side opposite the first side, and wherein the method further comprises:

placing a first alignment feature on the second side of the workpiece before molding the layer; and

marking the layer with a second alignment feature.

12. The method of claim 8 wherein:

attaching the free second conductive balls comprises coupling the free second conductive balls to the generally flat surfaces of the first conductive balls.

13. The method of claim 8 , further comprising:

cutting the workpiece to separate the individual dies; and

coupling a separated die to a support member without placing underfill material between the second conductive balls.

14. The method of claim 8 wherein:

the individual microelectronic dies comprise the terminals; and

forming the first conductive balls comprises placing the first conductive balls on the terminals of the die.

15. The method of claim 8 , further comprising constructing a redistribution structure on the workpiece, the redistribution structure including the terminals, wherein forming the first conductive balls on the terminals comprises placing the first conductive balls on the terminals of the redistribution structure.

16. A method of forming a plurality of microelectronic devices on a semiconductor workpiece, the method comprising:

constructing a redistribution structure on a first side of a semiconductor workpiece including a plurality of terminals;

providing an alignment feature on a second side of the semiconductor workpiece;

forming a plurality of first conductive balls on the redistribution structure with the first conductive balls projecting from the redistribution structure, individual conductive balls having a proximal portion proximate to the semiconductor workpiece and a distal portion opposite the proximal portion;

molding a protective layer onto the redistribution structure with the protective layer covering only a portion of the individual first conductive balls;

reconfiguring the first conductive balls by heating to make the distal portions of the conductive balls generally flat without removing material from the conductive balls, such that a top surface of the plurality of conductive balls located opposite the corresponding terminals are reshaped to include a flat surface spaced apart from the protective layer, wherein a diameter of the flat distal portions of the individual first conductive balls is smaller than a corresponding aperture in the second surface of the protective layer; and

aligning and attaching a plurality of second conductive balls on the flat surface of corresponding first conductive balls based on the alignment feature.

17. The method of claim 16 wherein the alignment feature comprises a first alignment feature, and wherein the method further comprises:

marking the protective layer with a second alignment feature.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →