Method for planarizing semiconductor device
View Patent ↗A method for planarizing a semiconductor device includes steps herein. A substrate is provided, on which a stop layer is formed. A trench is formed in the substrate. A first semiconductor film is deposited conformally on the stop layer and the trench. A second semiconductor film is deposited to fill the trench and cover the first semiconductor film. A chemical-mechanical polishing process is performed until the stop layer is exposed. A removal rate of the chemical-mechanical polishing process on the first semiconductor film is higher than that on the second semiconductor film. The first dielectric layer on the substrate selectively is removed.
1. A method for planarizing a semiconductor device, comprising steps of:
providing a substrate, on which a stop layer is formed;
forming a trench in said substrate;
depositing a U-shaped first semiconductor film conformally on said stop layer and said trench;
depositing a second semiconductor film to fill said trench and cover said U-shaped first semiconductor film; and
performing a chemical-mechanical polishing (CMP) process until said stop layer is exposed;
wherein a removal rate of said CMP process on said U-shaped first semiconductor film is higher than a removal rate of said CMP process on said second semiconductor film, and wherein said U-shaped first semiconductor film is U-shaped in said trench.
2. The method of claim 1 , further comprising a step, prior to forming said stop layer, of:
forming a pad oxide on said substrate.
3. The method of claim 1 , further comprising a step, prior to depositing said U-shaped first semiconductor film, of:
forming a liner oxide conformally on said stop layer and said trench, respectively.
4. The method of claim 3 , further comprising a step, after forming said liner oxide, of:
anisotropically removing said liner oxide on said stop layer.
5. The method of claim 4 , wherein said liner oxide on said stop layer is removed by plasma-enhanced etching.
6. The method of claim 1 , wherein said stop layer comprises silicon nitride.
7. The method of claim 1 , wherein said stop layer has a thickness of about 1500 Å to 3000 Å.
8. The method of claim 7 , wherein said stop layer has a thickness of about 2400 Å.
9. The method of claim 1 , wherein said trench has a width of about 1 μm to 5 μm.
10. The method of claim 9 , wherein said trench has a width of about 2.8 μm.
11. The method of claim 1 , wherein said U-shaped first semiconductor film comprises undoped poly-silicon.
12. The method of claim 11 , wherein said chemical-mechanical polishing process uses a slurry comprising colloidal silicon dioxide, an organic chemical additive and water.
13. The method of claim 12 , wherein said removal rate of said CMP process on said U-shaped first semiconductor film is about 70 Å/sec to 130 Å/sec.
14. The method of claim 13 , wherein said removal rate of said CMP process on said U-shaped first semiconductor film is about is about 100 Å/sec.
15. The method of claim 1 , wherein said second semiconductor film comprises boron-doped poly-silicon or phosphorus-doped poly-silicon.
16. The method of claim 15 , wherein said CMP process uses a slurry comprising colloidal silicon dioxide, an organic chemical additive and water.
17. The method of claim 16 , wherein said removal rate of said CMP process on said second semiconductor film is about 30 Å/sec to 60 Å/sec.
18. The method of claim 17 , wherein said removal rate of said CMP process on said second semiconductor film is about 43.5 Å/sec.
19. The method of claim 1 , wherein said U-shaped first semiconductor film has a thickness of about 1000 Å to 5000 Å.
20. The method of claim 19 , wherein said U-shaped first semiconductor film has a thickness of about 3000 Å.