Package on package memory interface and configuration with error code correction

1. Information communication circuitry, comprising:

a first integrated circuit coupled to a second integrated circuit in a package on package configuration, the first integrated circuit comprising processing circuitry for communicating information bits, and wherein the information bits comprise data bits and error correction bits, the error correction bits indicate whether data bits are received correctly;

the second integrated circuit comprises a memory for receiving and storing a portion of the information bits; and

interfacing circuitry coupled to the first integrated circuit and second integrated circuit, and operable to:

determine whether to access a first region of the memory and a second region of the memory; and

selectively communicate along conductors between the first integrated circuit and the second integrated circuit:

data bits along the conductors when accessing the first region of the memory; and

data bits along a first set of the conductors and error correction bits along a second set of the conductors when accessing the second region of the memory.

2. The information communication circuitry of claim 1 wherein the number of conductors comprises 32 conductors and 32 data bits are communicated when accessing the first region of the memory.

3. The information communication circuitry of claim 1 wherein the number of conductors comprises 32 conductors and 16 data bits are communicated when accessing the second region of the memory.

4. The information communication circuitry of claim 3 wherein in 8 error correction bits are communicated when accessing the second region of the memory.

5. The information communication circuitry of claim 3 wherein in up to 8 error correction bits are communicated when accessing the second region of the memory.

6. The information communication circuitry of claim 1 wherein the first region stores non-critical data and wherein the second region stores critical data.

7. The information communication circuitry of claim 1 wherein the first integrated circuit is coupled to the memory.

8. The information communication circuitry of claim 1 wherein the first integrated circuit is further for coupling to at least one additional integrated circuit, comprising a memory, in a non-package on package configuration.

9. The information communication circuitry of claim 8 :

wherein the number of conductors provides a first set of conductors;

wherein the interface circuitry comprises a second set of conductors; and

wherein the interfacing circuitry is further for communicating data bits along the first set of conductors while concurrently communicating error correction bits along the second set of conductors.

10. The information communication circuitry of claim 9 :

wherein the first set of conductors is 32 conductors; and

wherein the second set of conductors is 8 conductors.

11. The information communication circuitry of claim 9 wherein the first integrated circuit and coupled second integrated circuit together fit within a volume of one cubic inch or less.

12. The information communication circuitry of claim 9 :

wherein the first set of conductors is 16 conductors; and

wherein the second set of conductors is 8 conductors.

13. The information communication circuitry of claim 1 and further comprising the second integrated circuit.

14. The information communication circuitry of claim 1 wherein the interfacing circuitry comprises a set of conductors and a multiplexer:

wherein the conductors and the multiplexer output only data bits when accessing the first region of the memory; and

wherein the conductors output data bits and the multiplexer outputs only error correction bits when accessing the second region of the memory.

15. The information communication circuitry of claim 1 wherein the information bits comprise automotive video information bits.

16. A method of communicating information bits between a first integrated circuit and a second integrated circuit in a package on package configuration, the method comprising:

receiving, by an interfacing circuitry, information bits from the first integrated circuit, the information bits comprising data bits and error correction bits, the error correction bits indicate whether data bits are received correctly;

determining, by the interfacing circuitry, whether to access a first region or a second region of memory in the second integrated circuit; and

selectively communicating, by the interfacing circuitry along conductors, between the first integrated circuit and the second integrated circuit:

data bits along the conductors when accessing a first region of memory in the second integrated circuit; and

data bits along a first set of the conductors and error correction bits along a second set of the conductors when accessing a second region of memory in the second integrated circuit.

17. The method of claim 16 wherein the number of conductors comprises 32 conductors and 32 data bits are communicated when accessing a first region of memory in the second integrated circuit.

18. The method of claim 16 wherein the number of conductors comprises 32 conductors and 16 data bits are communicated when accessing a second region of memory in the second integrated circuit.

19. The information communication circuitry of claim 1 wherein up to 8 error correction bits are communicated when accessing a second region of memory in the second integrated circuit.