Selective growth for high-aspect ration metal fill
An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.
1. A method comprising:
receiving a substrate having a gate structure disposed thereupon, wherein the gate structure includes a sacrificial portion;
removing the sacrificial portion to define a trench within the gate structure, wherein the trench has opposing side surfaces and a bottom surface defined thereupon;
selectively forming a material layer on the opposing side surfaces, wherein the bottom surface is free of the material layer; and
depositing a fill material of a gate electrode on the material layer and on the bottom surface within the trench.
2. The method of claim 1 , wherein the forming of the material layer includes depositing a metal using atomic layer deposition (ALD) and performing a plasma treatment of the metal using a carbon-containing gas.
3. The method of claim 1 , wherein the forming of the material layer includes a deposition process and an etching process configured to remove deposited material from the bottom surface.
4. The method of claim 1 , wherein the material layer is formed to a thickness of less than about 20 Å.
5. The method of claim 1 further comprising:
forming a barrier layer on the opposing side surfaces and on the bottom surface within the trench prior to the forming of the material layer, wherein the barrier layer has a different composition from the material layer.
6. The method of claim 1 , wherein the material layer includes a metal carbide.
7. The method of claim 1 , wherein the material layer includes a metal nitride.
8. The method of claim 1 , wherein the material layer and the fill material contain a metal in common.
9. The method of claim 1 further comprising:
forming a gate dielectric layer within the trench prior to the forming of the material layer.
10. A method of semiconductor fabrication, the method comprising:
receiving a substrate having a recess defined therein, wherein the recess has at least two opposing sidewalls and a bottom surface;
depositing a growth control material within the recess and on the at least two opposing sidewalls such that the bottom surface is free of the growth control material; and
deposing a fill material layer within the recess such that the fill material is disposed on the growth control material and on the bottom surface.
11. The method of claim 10 , wherein the growth control material includes at least one of a metal nitride or a metal carbide.
12. The method of claim 11 , wherein the growth control material and the fill material layer include at least one metal in common.
13. The method of claim 11 , wherein the depositing of the growth control material includes depositing a metal of the growth control material and performing a plasma treatment of the metal using at least one of a nitrogen-containing gas and a carbon-containing gas.
14. The method of claim 11 , wherein the forming of the growth control material includes a deposition process and an etching process configured to remove deposited material from the bottom surface.
15. The method of claim 11 , wherein the growth control material is formed to a thickness of less than about 20 Å.
16. A method of forming a non-planar device comprising:
receiving a substrate having a gate structure disposed thereupon, wherein the gate structure includes a sacrificial portion;
removing the sacrificial portion to define a trench within the gate structure, wherein the trench has opposing side surfaces and a bottom surface defined thereupon;
performing deposition and plasma treatment processes to selectively form a material layer on the opposing side surfaces; and
depositing a fill material of a gate electrode on the material layer and on the bottom surface within the trench, thereby forming the non-planar device.
17. The method of claim 16 , wherein the material layer includes a metal and the deposition includes depositing the metal using atomic layer deposition (ALD).
18. The method of claim 16 , wherein the plasma treatment process includes an etching process configured to remove deposited material from the bottom surface.
19. The method of claim 16 , further comprising:
forming a barrier layer on the opposing side surfaces and on the bottom surface within the trench prior to the forming of the material layer, wherein the barrier layer has a different composition from the material layer.
20. The method of claim 16 , further comprising:
forming a gate dielectric layer within the trench prior to the forming of the material layer.