IP Library › Granted Patent US 10,203,955
Granted Patent B2
US 10,203,955 · App. 14/588,247 · Granted Feb 12, 2019

Methods, apparatus, instructions and logic to provide vector packed tuple cross-comparison functionality

Inventors: Robert Valentine (Kiryat Tivon, IL); Christopher J. Hughes (Santa Clara, CA); Mark J. Charney (Lexington, MA); Zeev Sperber (Zichron Yackov, IL); Amit Gradstein (Binyamina, IL); Simon Rubanovich (Haifa, IL); Elmoustapha Ould-Ahmed-Vall (Chandler, AZ); Yuri Gebil (Nahariya, IL)
Assignee: Intel Corporation
G06F9/30036G06F9/30018G06F9/30021G06F9/3834
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Quick Facts
Patent No.
US 10,203,955
App. No.
14/588,247
Granted
Feb 12, 2019
Kind
B2
Abstract

Instructions and logic provide SIMD vector packed tuple cross-comparison functionality. Some processor embodiments include first and second registers with a variable plurality of data fields, each of the data fields to store an element of a first data type. The processor executes a SIMD instruction for vector packed tuple cross-comparison in some embodiments, which for each data field of a portion of data fields in a tuple of the first register, compares its corresponding element with every element of a corresponding portion of data fields in a tuple of the second register and sets a mask bit corresponding to each element of the second register portion, in a bit-mask corresponding to each unmasked element of the corresponding first register portion, according to the corresponding comparison. In some embodiments bit-masks are shifted by corresponding elements in data fields of a third register. The comparison type is indicated by an immediate operand.

Claims (45)

1. A processor comprising:

a first vector register to store, in each of a first plurality of n data fields, an element of a data type;

a second vector register or memory storage set to store, in each of a second plurality of n data fields corresponding to the first plurality of n data fields, an element of the data type;

a decode stage to decode an instruction specifying a vector packed tuple cross-comparison operation and a tuple size, wherein the first vector register comprises a first plurality of tuple-sized portions, wherein each of the first plurality of tuple-sized portions comprises multiple ones of the first plurality of n data fields, wherein the second vector register or memory storage comprises a second plurality of tuple-sized portions, wherein each of the second plurality of tuple-sized portions comprises multiple ones of the second plurality of n data fields, wherein the tuple-size indicates a number of the first plurality of n data fields in each of the first plurality of tuple-sized portions and a number of the second plurality of n data fields in each of the second plurality of tuple-sized portions, and wherein each of the first plurality of tuple-sized portions corresponds to one of the second plurality of tuple-sized portions; and

one or more execution units, responsive to the decoded instruction and for each of a first portion among the first plurality of tuple-sized portions and a second portion among the second plurality of tuple-sized portions that corresponds to the first portion, to:

for each data field in the first portion, compare the element stored in the data field with each element of the second portion and set a mask bit corresponding to each element of the second portion in a bit-mask corresponding to the element of the first portion according to the corresponding comparison.

2. The processor of claim 1 , wherein a type of comparison for the vector packed tuple cross-comparison operation is indicated by an immediate operand specified by the instruction.

3. The processor of claim 2 , wherein the type of comparison for the vector packed tuple cross-comparison operation comprises equal, less-than, less-than or equal, false, not equal, not less-than, not less-than or equal, or true.

4. The processor of claim 1 , wherein the tuple size is two, wherein the first plurality of tuple-sized portions comprises pairs of the first plurality of n data fields, wherein the second plurality of tuple-sized portions comprises pairs of the second plurality of n data fields, and wherein the vector packed tuple cross-comparison operation comprises a vector packed double cross-comparison operation to cross-compare the pairs of the first plurality of n data fields with corresponding ones of the pairs of the second plurality of n data fields.

5. The processor of claim 1 , wherein the tuple size is four, wherein the first plurality of tuple-sized portions comprises four-tuples of the first plurality of n data fields, wherein the second plurality of tuple-sized portions comprises four-tuples of the second plurality of n data fields, and wherein the vector packed tuple cross-comparison operation comprises a vector packed quadruple cross-comparison operation to cross-compare the four-tuples of the first plurality of n data fields with corresponding ones of the four-tuples of the second plurality of n data fields.

6. The processor of claim 1 , wherein the tuple size is eight, wherein the first plurality of tuple-sized portions comprises eight-tuples of the first plurality of n data fields, wherein the second plurality of tuple-sized portions comprises eight-tuples of the second plurality of n data fields, and wherein the vector packed tuple cross-comparison operation comprises a vector packed octuple cross-comparison operation to cross-compare the eight-tuples of the first plurality of n data fields with corresponding ones of the eight-tuples of the second plurality of n data fields.

7. The processor of claim 1 , wherein n is 64.

8. The processor of claim 1 , wherein n is 32.

9. The processor of claim 1 , wherein n is 16.

10. The processor of claim 1 , wherein n is 8.

11. The processor of claim 1 , wherein each of the first plurality of n data fields is 8 bits.

12. The processor of claim 1 , wherein each of the first plurality of n data fields is 16 bits.

13. The processor of claim 1 , wherein a number of mask bits corresponding to each element of the second portion comprises 2 bits.

14. The processor of claim 1 , wherein a number of mask bits corresponding to each element of the second portion comprises 4 bits.

15. The processor of claim 1 , wherein a number of mask bits corresponding to each element of the second portion comprises 8 bits.

16. The processor of claim 1 , wherein the instruction specifies a mask register operand having a bit to indicate whether each data field, respectively, of the first plurality of n data fields is masked or unmasked for comparison.

17. A method comprising:

storing, in each of a first plurality of n data fields of a first vector register, an element of a data type;

storing, in each of a second plurality of n data fields of a second vector register corresponding to the first plurality of n data fields, an element of the data type;

executing, in a processor, a single-instruction multiple-data (SIMD) instruction for vector packed tuple cross-comparison, wherein the first vector register comprises a first plurality of tuple-sized portions, wherein each of the first plurality of tuple-sized portions comprises multiple ones of the first plurality of n data fields, wherein the second vector register or memory storage comprises a second plurality of tuple-sized portions, wherein each of the second plurality of tuple-sized portions comprises multiple ones of the second plurality of n data fields, wherein the tuple-size indicates a number of the first plurality of n data fields in each of the first plurality of tuple-sized portions and a number of the second plurality of n data fields in each of the second plurality of tuple-sized portions, and wherein each of the first plurality of tuple-sized portions corresponds to one of the second plurality of tuple-sized portions; and

for each of a first portion among the first plurality of tuple-sized portions and a second portion among the second plurality of tuple-sized portions that corresponds to the first portion:

for each data field in the first portion, comparing the element stored in the data field with each element of the second portion and setting a mask bit corresponding to each element of the second portion in a bit-mask corresponding to the element of the first portion according to the corresponding comparison.

18. The method of claim 17 , wherein each element of the first portion is implicitly unmasked for comparison.

19. The method of claim 17 , wherein a number of bits of a mask register are set to one or zero to explicitly indicate that a corresponding element of the first portion is unmasked or masked respectively for comparison.

20. The method of claim 17 , wherein the tuple size is two, and wherein the first portion and the second portion each comprise two data fields.

21. The method of claim 17 , wherein the tuple size is four, and wherein the first portion and the second portion each comprise four data fields.

22. The method of claim 17 , wherein the tuple size is eight, and wherein the first portion and the second portion each comprise eight data fields.

23. A processing system comprising:

a memory; and

a plurality of processors each comprising:

a first vector register to store, in each of a first plurality of n data fields, an element of a data type;

a second vector register or memory storage set to store, in each of a second plurality of n data fields corresponding to the first plurality of n data fields, an element of the data type;

a decode stage to decode an instruction specifying a vector packed tuple cross-comparison operation and a tuple size, wherein the first vector register comprises a first plurality of tuple-sized portions, wherein each of the first plurality of tuple-sized portions comprises multiple ones of the first plurality of n data fields, wherein the second vector register or memory storage comprises a second plurality of tuple-sized portions, wherein each of the second plurality of tuple-sized portions comprises multiple ones of the second plurality of n data fields, wherein the tuple-size indicates a number of the first plurality of n data fields in each of the first plurality of tuple-sized portions and a number of the second plurality of n data fields in each of the second plurality of tuple-sized portions, and wherein each of the first plurality of tuple-sized portions corresponds to one of the second plurality of tuple-sized portions; and

one or more execution units, responsive to the decoded instruction and for each of a first portion among the first plurality of tuple-sized portions and a second portion among the second plurality of tuple-sized portions that corresponds to the first portion, to:

for each data field in the first portion, compare the element stored in the data field with each element of the second portion and set a mask bit corresponding to each element of the second portion in a bit-mask corresponding to the element of the first portion according to the corresponding comparison.

24. The processing system of claim 23 , wherein a type of comparison for the vector packed tuple cross-comparison operation is indicated by an immediate operand specified by the instruction.

25. The processing system of claim 24 , wherein the type of comparison for the vector packed tuple cross-comparison operation comprises equal, less-than, less-than or equal, false, not equal, not less-than, not less-than or equal, or true.

26. The processing system of claim 23 , wherein the tuple size is two, wherein the first plurality of tuple-sized portions comprises pairs of the first plurality of n data fields, wherein the second plurality of tuple-sized portions comprises pairs of the second plurality of n data fields, and wherein the vector packed tuple cross-comparison operation comprises a vector packed double cross-comparison operation to cross-compare the pairs of the first plurality of n data fields with corresponding ones of the pairs of the second plurality of n data fields.

27. The processing system of claim 23 , wherein the tuple size is four, wherein the first plurality of tuple-sized portions comprises four-tuples of the first plurality of n data fields, wherein the second plurality of tuple-sized portions comprises four-tuples of the second plurality of n data fields, and wherein the vector packed tuple cross-comparison operation comprises a vector packed quadruple cross-comparison operation to cross-compare the four-tuples of the first plurality of n data fields with corresponding ones of the four-tuples of the second plurality of n data fields.

28. The processing system of claim 23 , wherein the tuple size is eight, wherein the first plurality of tuple-sized portions comprises eight-tuples of the first plurality of n data fields, wherein the second plurality of tuple-sized portions comprises eight-tuples of the second plurality of n data fields, and wherein the vector packed tuple cross-comparison operation comprises a vector packed octuple cross-comparison operation to cross-compare the eight-tuples of the first plurality of n data fields with corresponding ones of the eight-tuples of the second plurality of n data fields.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2015
From: VALENTINE, ROBERT; SPERBER, ZEEV; GRADSTEIN, AMIT; RUBANOVICH, SIMON; GEBIL, YURI; HUGHES, CHRISTOPHER J; CHARNEY, MARK J; OULD-AHMED-VALL, ELMOUSTAPHA
To: INTEL CORPORATION
Reel/Frame 036721/0809 →
Continuity (1)
Related Publication 20160188336A1 · Jun 30, 2016