Semiconductor devices and methods of forming the same

1. A method of forming semiconductor device, comprising:

preparing a substrate including a cell array region having a first active region delimited by a field isolation region, and a peripheral circuit region having a second active region, the first active region including a first source/drain region and second source/drain regions at opposite sides of the first source/drain region;

forming a first wiring film and an etching buffer film in the cell array region and the peripheral circuit region;

forming a contact hole by patterning the etching buffer film and the first wiring film to at least partially expose the first source/drain region and the field isolation region adjacent to the first source/drain region;

forming a bit line contact in the contact hole so as to be in contact with the first source/drain region;

forming a second wiring film over the substrate; and

forming a bit line in the cell array region and a peripheral gate in the peripheral circuit region by patterning the second wiring film, the etching buffer film, and the first wiring film,

the forming a bit line including patterning the second wiring film and the bit line contact on the first source/drain region in the cell array region, and

the forming a peripheral gate including patterning the second wiring film to at least partially expose the etching buffer film in the peripheral circuit region.

2. The method of claim 1 , wherein the forming a bit line further comprises patterning the second wiring film to at least partially expose the etching buffer film in the cell array region.

3. The method of claim 2 , wherein the patterning the second wiring film and the bit line contact on the first source/drain region in the cell array region further comprises at least partially exposing the contact hole so as to expose at least a part of side walls of at least one selected from the etching buffer film, the first wiring film and a combination thereof.

4. The method of claim 3 , wherein the forming a bit line in the cell array region and a peripheral gate in the peripheral circuit region further comprises

partially exposing an adjacent field isolation region by additionally patterning the bit line contact on the first source/drain region in the cell array region; and

patterning the exposed etching buffer film and the first wiring film in the cell array region and the peripheral circuit region.

5. The method of claim 1 , wherein

the first wiring film comprises a semiconductor film, and

the forming a second wiring film comprises forming at least one of an ohmic barrier film, a metal silicide film, a metal film, and combinations thereof,

the ohmic barrier film including at least one selected from a titanium silicon nitride, a tungsten silicon nitride, a tantalum silicon nitride, a titanium silicide, and combinations thereof.

6. The method of claim 1 , wherein the etching buffer film comprises a lanthanum film, a lanthanum oxide, or a combination thereof.

7. A method of forming semiconductor device, comprising:

preparing a substrate including a cell array region having an active region and a peripheral circuit region;

forming a first wiring film and an etching buffer film in the cell array region and a peripheral circuit region;

forming a bit line contact so as to be in contact with the active region by passing through the etching buffer film and the first wiring film;

forming a second wiring film on the etching buffer film and the bit line contact; and

forming a bit line in the cell array region and a peripheral gate in the peripheral circuit region by patterning the second wiring film, the bit line contact, the etching buffer film, and the first wiring film,

the patterning the second wiring film and the bit line contact is performed so as to prevent the first wiring film from being etched by the etching buffer film.

8. A method of forming a semiconductor device, comprising:

providing a substrate having a peripheral circuit region and a cell array region, the cell array region having a source/drain region;

forming a lower wiring structure and an etching buffer structure over the peripheral circuit region and the cell array region;

forming a bit line contact extending through the etching buffer structure and the lower wiring structure to the source/drain region;

forming an upper wiring structure over the peripheral circuit region and the bit line contact; and

forming a bit line in the cell array region and a peripheral gate in the peripheral circuit region by simultaneously patterning the upper wiring structure, the bit line contact, the etching buffer structure, and the lower wiring structure.

9. The method of claim 8 , wherein the forming the upper wiring structure over the peripheral circuit region and the bit line contact includes partially exposing the etching buffer structure in the peripheral region and the cell array region.

10. The method of claim 8 , further comprising:

forming an ohmic barrier pattern over the peripheral region and the cell array region using the etching buffer structure as an etch buffer, prior to the forming a bit line.

11. The method of claim 10 , wherein the etching buffer structure has at least one selected from (i) a higher etching selectivity and (ii) a smaller thickness than the ohmic barrier pattern.

12. The method of claim 10 , wherein

the etching buffer structure is formed of at least one lanthanoid, and

the ohmic barrier pattern is formed of at least one metal silicide.