Memory device

1. A memory device, comprising:

a peripheral circuit region including a plurality of circuit elements disposed on a first substrate, the first substrate including:

a first region on which the plurality of circuit elements are disposed, and

a second region extending from an upper surface of the first region in a direction perpendicular thereto;

a cell region including at least one channel region extending from an upper surface of a second substrate disposed on the first substrate in a direction perpendicular to the upper surface of the second substrate, the second region of the first substrate extending from the upper surface of the first region to contact a lower surface of the second substrate; and

a plurality of gate electrode layers and a plurality of insulating layers stacked on the second substrate to be adjacent to the at least one channel region,

wherein at least a portion of the first substrate contacts the second substrate, and the first substrate and the second substrate provide a single substrate, and

wherein a cross-sectional width of the upper surface of the second substrate is less than or equal to 30 times a cross-sectional width of the second region of the first substrate parallel to the upper surface of the second substrate, the first and second regions of the first substrate including a same material.

2. The memory device of claim 1 , wherein the second region includes a plurality of second regions, a cross-section of each second region connected to the first region has a shape of an inverted T.

3. The memory device of claim 1 , wherein a cross-sectional area of the upper surface of the second substrate is smaller than a cross-sectional area of the first region substantially parallel to the upper surface of the second substrate.

4. The memory device of claim 1 , wherein at least one of the plurality of circuit elements is electrically connected to at least one of the plurality of gate electrode layers.

5. The memory device of claim 1 , wherein each of the first substrate and the second substrate consists essentially of single crystal silicon, the first and second substrates being directly connected to each other to provide a single substrate including single crystal silicon.

6. The memory device of claim 1 , wherein the second substrate and the first region of the first substrate are spaced apart and parallel to each other, the second region of the first substrate connecting the first and second substrates to each other and being perpendicular to each of the second substrate and the first region of the first substrate.

7. The memory device of claim 1 , wherein a space is defined between the second substrate and the first region of the first substrate, the space being adjacent to the second region of the first substrate, and a peripheral region insulating layer being positioned in the space to contact directly at least each of the first and second regions of the first substrate.

8. A memory device, comprising:

a peripheral circuit region including a plurality of circuit elements disposed on a first substrate, the first substrate including:

a first region on which the plurality of circuit elements are disposed, and

a second region extending from an upper surface of the first region in a direction perpendicular thereto;

a cell region including at least one channel region extending from an upper surface of a second substrate disposed on the first substrate in a direction perpendicular to the upper surface of the second substrate, the second region of the first substrate extending from the upper surface of the first region to contact a lower surface of the second substrate;

a plurality of gate electrode layers and a plurality of insulating layers stacked on the second substrate to be adjacent to the at least one channel region; and

a peripheral region insulating layer disposed on the first region to fill a space between the first substrate and the second substrate, the second region of the first substrate extending through the peripheral region insulating layer to contact the lower surface of the second substrate,

wherein at least a portion of the first substrate contacts the second substrate, and the first substrate and the second substrate provide a single substrate.

9. The memory device of claim 8 , wherein the peripheral region insulating layer includes a high density plasma (HDP) oxide film.

10. The memory device of claim 8 , wherein an upper surface of the peripheral region insulating layer is substantially parallel to the upper surface of the second substrate.

11. The memory device of claim 8 , wherein an upper surface of the peripheral region insulating layer is substantially coplanar to the upper surface of the second substrate.

12. A memory device, comprising:

a first substrate;

a second substrate disposed on the first substrate;

a plurality of transistors disposed on the second substrate and defining memory cells;

a plurality of circuit elements disposed on the first substrate, the first substrate and the second substrate providing a single substrate including single crystal silicon; and

a peripheral region insulating layer disposed between the first substrate and the second substrate to cover the plurality of circuit elements,

wherein the first substrate includes:

a first region on which the plurality of circuit elements are disposed; and

a second region extending from an upper surface of the first region in a direction perpendicular thereto to contact a lower surface of the second substrate.

13. The memory device of claim 12 , wherein a cross-sectional width of the second substrate is less than or equal to 30 times a cross-sectional width of the second region.