Apparatus And Methods For High-Density Chip Connectivity
Self-alignment structures, such as micro-balls and V-grooves, may be formed on chips made by different processes. The self-alignment structures may be aligned to mask layers within an accuracy of one-half the smallest feature size inside a chip. For example, the alignment structures can align an array of pads having a pitch of 0.6 microns, compared to a pitch of 100 microns available with today's Ball Grid Array (BGA) technology. As a result, circuits in the mated chips can communicate via the pads with the same speed or clock frequency as if in a single chip. For example, clock rates between interconnected chips can be increased from 100 MHz to 4 GHz due to low capacitance of the interconnected pads. Because high-density arrays of pads can interconnect chips, chips can be made smaller, thereby reducing cost of chips by order(s) of magnitude.
1 . An electronic chip, comprising:
a substrate;
an electronic circuit formed on the substrate; and
a plurality of conductive pads formed on the substrate and connected to the electronic circuit, the conductive pads having a pitch less than approximately 100 microns.
2 . The electronic chip of claim 1 , further comprising at least one alignment structure formed on the substrate.
3 . The electronic chip of claim 2 , wherein the at least one alignment structure includes an indentation.
4 . The electronic chip of claim 3 , wherein the indentation includes tapering surfaces into the substrate.
5 . The electronic chip of claim 2 , wherein the at least one alignment structure includes a semi-hemispherical shape.
6 . The electronic chip of claim 2 , wherein the at least one alignment structure includes a circular post.
7 . The electronic chip of claim 1 , wherein the conductive pads have a maximum surface area less than approximately 10 square microns.
8 . The electronic chip of claim 7 , wherein the conductive pads have a maximum surface area less than approximately 0.5 square microns.
9 . The electronic chip of claim 1 , wherein the electronic circuit includes memory elements.
10 . The electronic chip of claim 1 , wherein the electronic circuit includes signal or data processing elements.
11 . An electronic chip, comprising:
a substrate;
an electronic circuit formed on the substrate; and
a plurality of conductive pads formed on the substrate and connected to the electronic circuit, the conductive pads covering a surface area less than approximately 10 square microns on the substrate.
12 . The electronic chip of claim 11 , wherein the conductive pads have a maximum surface area less than approximately 0.5 square microns.
13 . The electronic chip of claim 11 , further comprising at least one alignment structure formed on the substrate.
14 . The electronic chip of claim 13 , wherein the at least one alignment structure defines an indentation.
15 . The electronic chip of claim 14 , wherein the indentation includes tapering surfaces into the substrate.
16 . The electronic chip of claim 13 , wherein the at least one alignment structure includes a semi-hemispherical shape.
17 . The electronic chip of claim 13 , wherein the at least one alignment structure includes a circular post.
18 . The electronic chip of claim 11 , wherein the electronic circuit includes memory elements.
19 . The electronic chip of claim 11 , wherein the electronic circuit includes signal or data processing elements.
20 . The electronic chip of claim 13 , wherein the at least one alignment structure is configured to be positionally aligned with at least another alignment structure of another electronic chip such that at least a portion of the conductive pads is in contact with one or more conductive pads of the another electronic chip when the electronic chip and the another electronic chip are bonded together.