Signal modulation circuit
Provided is a circuit which can correct an output state in real time and reduce influences of distortion/noise components generated by a delay device. A signal modulation circuit includes a subtractor, an integrator, a phase inverting circuit, a DFF for while inserting a zero level at timing synchronous with the clock signal, delaying and quantizing the signal, a ternary signal generating circuit for generating a ternary signal for selectively driving a load connected to a single power supply into ternary conductive states including a positive current on-state, a negative current on-state, and an off-state, a driver circuit for generating a driving signal for driving a load, and a feedback circuit for feeding back the driving signal from the driver circuit to the input signal.
1. A signal modulation circuit for performing delta sigma modulation on an input signal in synchronization with a clock signal to output the modulated signal, the circuit comprising:
a subtractor for calculating a difference between the input signal and a feedback signal;
an integrator for integrating an output from the subtractor;
a quantizer for, while inserting a zero level into the signal integrated by the integrator at timing synchronous with the clock signal in order to maintain a pulse width, delaying the signal and quantizing the signal;
a driver circuit for generating a driving signal for driving a load based on the signal from the quantizer; and
a feedback circuit for feeding back the driving signal from the driver circuit to the input signal.
2. A signal modulation circuit for performing delta sigma modulation on an input signal in synchronization with a clock signal to output the modulated signal, the circuit comprising:
a subtractor for calculating a difference between the input signal and a feedback signal;
an integrator for integrating an output from the subtractor;
a phase inverting circuit for inverting a phase of the signal integrated by the integrator;
a first quantizer for, while inserting a zero level into the signal integrated by the integrator at timing synchronous with the clock signal in order to maintain a pulse width, delaying and quantizing the signal;
a second quantizer for, while inserting a zero level into the signal whose phase is inverted by the phase inverting circuit at the timing synchronous with the clock signal in order to maintain a pulse width, delaying and quantizing the signal;
a ternary signal generating circuit for generating a ternary signal for selectively driving a load connected to a single power supply into ternary conductive states including a positive current on-state, a negative current on-state, and an off-state using the signal from the first quantizer and the signal from the second quantizer;
a driver circuit for generating a driving signal for driving the load based on the signal from the ternary signal generating circuit; and
a feedback circuit for feeding back the driving signal from the driver circuit to the input signal.