Arrays of memory cells and methods of forming an array of vertically stacked tiers of memory cells
View Patent ↗An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers and a plurality of horizontally oriented global sense lines elevationally outward of the tiers. A plurality of select transistors is elevationally inward of the tiers. A plurality of pairs of local first and second vertical lines extends through the tiers. The local first vertical line within individual of the pairs is in conductive connection with one of the global sense lines and in conductive connection with one of the source/drain regions of one of the select transistors. The local second vertical line is in conductive connection with the other source/drain region of the one select transistor. Individual memory cells include a crossing one of the local second vertical lines and one of the horizontal access lines and programmable material there-between. Other aspects and implementations, including methods, are disclosed.
1. An array of memory cells, comprising:
a plurality of crossing access lines and sense lines elevationally over a substrate surface;
a plurality of pairs of vertical lines extending vertically between the substrate surface and the sense lines, each of the pairs of vertical lines comprising a first vertical line and a second vertical line having opposing vertical sidewalls, each first vertical line of each pair of lines comprised by the plurality extending to a first elevation above the substrate surface and each second vertical line of each pair of vertical lines comprised by the plurality extending to a second elevation above the substrate surface, the first and second elevations differing relative to one another;
programmable material extending along each of the opposing vertical sidewalls of each of the second vertical lines, the programmable material comprising one or more members of the group consisting of oxide material having ions diffused therein, multi-resistive state metal oxide comprising material, polymer material and memristive material, the programmable material contacting the access lines only along vertical surfaces of the access lines; and
two select transistors having respective gates that are wired in parallel to selectively enable current flow in each sense line, the respective gates being laterally spaced from one another by dielectric material and current conductive material.
2. The array of claim 1 wherein the gates are hard-wired together.
3. The array of claim 1 wherein the gates are soft-wired together.
4. The array of claim 1 wherein the access lines are arranged in vertically stacked tiers individually comprising a plurality of access lines.
5. The array of claim 1 wherein the select transistors are elevationally inward of all of the access lines within the array.
6. The array of claim 5 wherein the access lines are arranged in vertically stacked tiers individually comprising a plurality of access lines.
7. The array of claim 1 wherein the sense lines comprise local lines within the array, and further comprising global lines within the array in switchable conductive connection with the local lines.
8. The array of claim 7 wherein the global lines are elevationally outward of all of the access lines within the array.
9. The array of claim 8 wherein the select transistors are elevationally inward of all of the access lines within the array.