Semiconductor integrated circuit apparatus and manufacturing method for same
View Patent ↗A semiconductor integrated circuit apparatus and a manufacturing method for the same are provided in such a manner that a leak current caused by a ballast resistor is reduced, and at the same time, the inconsistency in the leak current is reduced. The peak impurity concentration of the ballast resistors is made smaller than the peak impurity concentration in the extension regions, and the depth of the ballast resistors is made greater than the depth of the extension regions.
1. A semiconductor integrated circuit apparatus, comprising a first insulated gate transistor that includes: a first well region of a first conductivity type in a semiconductor substrate; a first gate electrode provide on the first well region with a first gate insulating film in between; a first channel dope region of the first conductivity type provided beneath the first gate electrode; a first extension region of a second conductivity type that is a conductivity type opposite to the first conductivity type, a first source region of the second conductivity type, and a first drain region of the second conductivity type provided on both sides of the first gate electrode; and a first ballast resistor of the second conductivity type that separates the first drain region, wherein a peak impurity concentration of the first ballast resistor is lower than a peak impurity concentration of the first extension region, and a depth of the first ballast resistor is greater than a depth of the first extension region.
2. The semiconductor integrated circuit apparatus according to claim 1 , characterized by further including an insulating film pattern that becomes a salicide block directly above the first ballast resistor.
3. The semiconductor integrated circuit apparatus according to claim 1 , further comprises a second insulated gate transistor of which a drive voltage is higher than a drive voltage of the first insulated gate transistor, that includes: a second well region of the first conductivity type in the semiconductor substrate, a second gate electrode provided in the second well region with a second gate insulating film in between; a low concentration source/drain region of the second conductivity type, a second source region of the second conductivity type of which an impurity concentration is higher than an impurity concentration of the low concentration source/drain region, and a second drain region of the second conductivity type of which an impurity concentration is higher than the impurity concentration of the low concentration source/drain region provided on both sides of the second gate electrode, characterized in that an impurity concentration of the first ballast resistor is the same or higher than the impurity concentration of the low concentration source/drain region, and the depth of the first ballast resistor is the same or greater than a depth of the low concentration source/drain region.
4. The semiconductor integrated circuit apparatus according to claim 1 , further comprises a third insulated gate transistor of which a drive voltage is the same as the drive voltage of the first insulated gate transistor, that includes: a third well region of the first conductivity type in the semiconductor substrate, a third gate electrode provided in the third well region with a third gate insulating film in between; a second channel dope region of the first conductivity type provided beneath the third gate electrode; and a second extension region of the second conductivity type, a third source region of the second conductivity type, and a third drain region of the second conductivity type provided on the two sides of the third gate electrode.
5. The semiconductor integrated circuit apparatus according to claim 1 , further includes a number of flash memory elements with a floating gate in a fourth well region of the first conductivity type in the semiconductor substrate.
6. The semiconductor integrated circuit apparatus according to claim 1 , further includes a fourth insulated gate transistor that comprises: a fourth well region of the second conductivity type in the semiconductor substrate, a fourth gate electrode provided in the first well region of the second conductivity type with a fourth gate insulating film in between; a third channel dope region of the second conductivity type provided beneath the fourth gate electrode; a third extension region of the first conductivity type, a fourth source region of the first conductivity type, and a fourth drain region of the first conductivity type provided on the two sides of the fourth gate electrode; and a second ballast resistor of the first conductivity type that separates the fourth drain region of the first conductivity type, the impurity concentration of the second conductivity type of the first ballast resistor has the same value gained by subtracting the value of the impurity concentration of the second conductivity type in the first well region of the second conductivity type from the value of the impurity concentration of the second conductivity type in the third channel dope region, the depth of the first ballast resistor is the same as the depth of the third channel dope region, the impurity concentration of the first conductivity type of the second ballast resistor has the same value gained by subtracting the value of the impurity concentration of the first conductivity type in the first well region of the first conductivity type from the value of the impurity concentration of the first conductivity type in the first channel dope region, and the depth of the second ballast resistor is the same as the depth of the first channel dope region.
7. A semiconductor integrated circuit apparatus, comprising a first insulated gate transistor that includes: a first well region of a first conductivity type in a semiconductor substrate; a first gate electrode provided on the first well region with a first gate insulating film in between; a first channel dope region of the first conductivity type provided beneath the first gate electrode; a first extension region of a second conductivity type that is a conductivity type opposite to the first conductivity type, a first source region of the second conductivity type, and a first drain region of the second conductivity type provided on both sides of the first gate electrode; and a first ballast resistor of the second conductivity type that separates the first drain region, wherein a peak impurity concentration of the first ballast resistor is lower than a peak impurity concentration of the first extension region, and a depth of the first ballast resistor is greater than a depth of the first extension region, and wherein a difference between the peak impurity concentration of the first ballast resistor and a peak impurity concentration of the first well region is lower than a difference between the peak impurity concentration of the first extension region and a peak impurity concentration of the first channel dope region.