Semiconductor device layout, memory device layout, and method of manufacturing semiconductor device
A layout of a semiconductor device includes active area regions, gate electrodes crossing the plurality of active area regions, spacers along sides of the corresponding plurality of gate electrodes, a first contact patterning region, a second contact patterning region, and a contact area. The first contact patterning region overlaps at least one active area region among the plurality of active area regions, at least one gate electrode among the plurality of gate electrodes, and at least one spacer among the plurality of spacers, the at least one spacer corresponding to the at least one gate electrode. The second contact patterning region overlaps a portion of the first contact patterning region. The contact area overlaps the at least one active area region. A boundary of the contact area is defined by boundaries of the first contact patterning region, the second contact patterning region and the at least one spacer.
1. A layout of a semiconductor device, the layout stored on a non-transitory computer-readable medium and comprising:
a plurality of active area regions;
a plurality of gate electrodes crossing the plurality of active area regions;
a plurality of spacers along sides of the corresponding plurality of gate electrodes;
a first contact patterning region overlapping
at least one active area region among the plurality of active area regions,
at least one gate electrode among the plurality of gate electrodes, and
at least one spacer among the plurality of spacers, the at least one spacer corresponding to the at least one gate electrode;
a second contact patterning region overlapping a portion of the first contact patterning region; and
a contact area overlapping the at least one active area region, a boundary of the contact area defined by boundaries of the first contact patterning region, the second contact patterning region and the at least one spacer.
2. The layout of claim 1 , wherein
the boundary of the contact area is further defined by a boundary of the at least one gate electrode.
3. The layout of claim 1 , wherein
the at least one gate electrode comprises adjacent first and second gate electrodes among the plurality of gate electrodes,
the at least one spacer comprises adjacent first and second spacers among the plurality of spacers, the first spacer corresponding to the first gate electrode, and the second spacer corresponding to the second gate electrode, and
the contact area comprises first through fourth edges, the first edge opposite the second edge, the third edge opposite the fourth edge,
the first edge corresponding to an edge of the first spacer,
the second edge corresponding to an edge of the second spacer,
the third edge corresponding to an edge of the first contact patterning region, and
the fourth edge corresponding to an edge of the second contact patterning region.
4. The layout of claim 1 , further comprising:
a further contact area overlapping the at least one active area region,
wherein
the plurality of gate electrodes comprises adjacent first and second gate electrodes,
the plurality of spacers comprises adjacent first and second spacers, the first spacer corresponding to the first gate electrode, and the second spacer corresponding to the second gate electrode, and
the further contact area comprises first through fourth edges, the first edge opposite the second edge, the third edge opposite the fourth edge,
the first edge corresponding to an edge of the first spacer,
the second edge corresponding to an edge of the second spacer, and
the third and fourth edges corresponding to opposite edges of the first contact patterning region.
5. The layout of claim 1 , wherein
the first contact patterning region is configured to form an opening in a first photoresist layer, and
the second contact patterning region is configured to form a region filled with a photoresist material in a second photoresist layer.
6. The layout of claim 1 , wherein
the first contact patterning region comprises a clear tone pattern, and
the second contact patterning region comprises a dark tone pattern.
7. The layout of claim 1 , wherein
the at least one active area region comprises adjacent first and second active area regions among the plurality of active area regions,
the at least one gate electrode comprises first, second and third gate electrodes among the plurality of gate electrodes, the second gate electrode adjacent and between the first and third gate electrodes,
the at least one spacer comprises first through fourth spacers among the plurality of spacers, the first spacer corresponding to the first gate electrode, the second and third spacers corresponding to the second gate electrode, the fourth spacer corresponding to the third gate electrode, the first spacer facing the second spacer, the third spacer facing the fourth spacer, and
the contact area is a first contact area overlapping the first active area region, the first contact area comprising first through fourth edges, the first edge opposite the second edge, the third edge opposite the fourth edge,
the first edge corresponding to an edge of the first spacer,
the second edge corresponding to an edge of the second spacer,
the third edge corresponding to a first edge of the first contact patterning region, and
the fourth edge corresponding to a first edge of the second contact patterning region.
8. The layout of claim 7 , further comprising:
a second contact area overlapping the second active area region, the second contact area comprising first through fourth edges, the first edge of the second contact area opposite the second edge of the second contact area, the third edge of the second contact area opposite the fourth edge of the second contact area,
the first edge of the second contact area corresponding to the edge of the first spacer,
the second edge of the second contact area corresponding to the edge of the second spacer,
the third edge of the second contact area corresponding to a second edge of the first contact patterning region, and
the fourth edge of the second contact area corresponding to a second edge of the second contact patterning region.
9. The layout of claim 8 , further comprising:
a third contact area overlapping the first and second active area regions, the third contact area comprising first through fourth edges, the first edge of the third contact area opposite the second edge of the third contact area, the third edge of the third contact area opposite the fourth edge of the third contact area,
the first edge of the third contact area corresponding to an edge of the third spacer,
the second edge of the third contact area corresponding to an edge of the fourth spacer,
the third edge of the third contact area corresponding to the first edge of the first contact patterning region, and
the fourth edge of the third contact area corresponding to the second edge of the first contact patterning region.
10. The layout of claim 9 , wherein
the second gate electrode and the first active area region define a first transistor,
the second gate electrode and the second active area region define a second transistor, and
the third contact area coupling a source or a drain of the first transistor with a source or a drain of the second transistor.
11. A layout of a memory device, the layout stored on a non-transitory computer-readable medium and comprising:
a plurality of memory cells, each memory cell of the plurality of memory cells comprising first and second portions, each portion of the first and second portions comprising:
a first transistor coupled between a first power supply node and a storage node;
a second transistor coupled between a second power supply node and the storage node;
a third transistor coupled between a bitline node and the storage node;
a first contact patterning region covering active area regions, gate electrodes and spacers of the first, second and third transistors, the first contact patterning region covering less than an entirety of the each portion; and
a second contact patterning region overlapping the first contact patterning region, the second contact patterning region being between the first power supply node and the second power supply node.
12. The layout of claim 11 , wherein
the first contact patterning region comprises a clear tone pattern, and
the second contact patterning region comprises a dark tone pattern.
13. The layout of claim 11 , wherein, in each portion of the first and second portions,
the active area regions comprise a first active area region of the first and third transistors, and a second active area region of the second transistor,
the gate electrodes comprise a first gate electrode of the first and second transistors, and a second gate electrode of the third transistor,
the spacers comprise first and second spacers on opposite sides of the first gate electrode, and third and fourth spacers on opposite sides of the second gate electrode.
14. The layout of claim 13 , wherein, in each portion of the first and second portions,
edges of the first power supply node are defined by corresponding edges of the first contact patterning region, the second contact patterning region and the first spacer,
edges of the second power supply node are defined by corresponding edges of the first contact patterning region, the second contact patterning region and the first spacer, and
edges of the storage node are defined by corresponding edges of the first contact patterning region, the second spacer and the third spacer.
15. The layout of claim 13 , wherein, in each portion of the first and second portions,
edges of the bitline node are defined by corresponding edges of the first contact patterning region and the fourth spacer.
16. The layout of claim 13 , wherein each portion of the first and second portions further comprises:
a third contact patterning region overlapping the first contact patterning region, wherein edges of the bitline node are defined by corresponding edges of the first contact patterning region, the third contact patterning region and the fourth spacer.
17. The layout of claim 13 , wherein each memory cell of the plurality of memory cells further comprises:
a contact area coupling the storage node of one of the first and second portions to the first gate electrode of the other of the first and second portions.
18. A layout of a semiconductor device, the layout stored on a non-transitory computer-readable medium and comprising:
a first active area region;
a second active area region;
a first gate electrode crossing the first active area region and the second active area region;
a second gate electrode crossing the first active area region and the second active area region;
a first spacer along a side of the first gate electrode;
a second spacer along a side of the second gate electrode;
a first contact patterning region overlapping the first active area region, the second active area region, the first gate electrode, the second gate electrode, the first spacer, and the second spacer;
a second contact patterning region overlapping a portion of the first contact patterning region;
a first contact area overlapping the first active area region; and
a second contact area overlapping the second active area region,
wherein each of the first contact area and the second contact area has a boundary defined by boundaries of the first contact patterning region, the second contact patterning region, the first spacer, and the second spacer.
19. The layout of claim 18 , wherein each of the first active area region and the second active area comprises a fin.
20. The layout of claim 18 , wherein
the first contact patterning region comprises a clear tone pattern, and
the second contact patterning region comprises a dark tone pattern.