Semiconductor device and method of fabricating the same
A semiconductor device includes a first multi-channel active pattern defined by a field insulating layer and extending along a first direction, the first multi-channel active pattern including a first portion having a top surface protruding further in an upward direction than a top surface of the field insulating layer and a second portion on both sides of the first portion, the second portion having sidewalls with a continuous profile and a top surface protruding further in the upward direction than the top surface of the field insulating layer and protruding in the upward direction less than the top surface of the first portion, a gate electrode on the first portion of the first multi-channel active pattern and extending along a second direction different from the first direction, and a first source/drain region on the second portion of the first multi-channel active pattern and contacting the field insulating layer.
1. A semiconductor device comprising:
a first multi-channel active pattern defined by a field insulating layer and extending along a first direction, the first multi-channel active pattern including,
a first portion having a top surface protruding further in an upward direction than a top surface of the field insulating layer, and
a second portion on both sides of the first portion, the second portion having a top surface protruding further in the upward direction than the top surface of the field insulating layer and protruding in the upward direction less than the top surface of the first portion, the second portion having sidewalls with a continuous profile;
a gate electrode on the first portion of the first multi-channel active pattern, the gate electrode extending along a second direction different from the first direction; and
a first source/drain region on the second portion of the first multi-channel active pattern and contacting the field insulating layer.
2. The semiconductor device of claim 1 , wherein
the entire second portion protrudes further in the upward direction than the top surface of the field insulating layer, and
the first source/drain region is formed on the top surface and sidewalls of the second portion.
3. The semiconductor device of claim 1 , wherein
the entire second portion protrudes further in the upward direction than the top surface of the field insulating layer, and
the first source/drain region directly contacts the entire second portion.
4. The semiconductor device of claim 3 , wherein the first source/drain region contacts the top surface of the field insulating layer.
5. The semiconductor device of claim 1 , further comprising:
fin spacers on a part of the sidewalls of the second portion protruding further in the upward direction than the top surface of the field insulating layer.
6. The semiconductor device of claim 5 , wherein a part of the second portion protrudes further in the upward direction than the fin spacers.
7. The semiconductor device of claim 5 , wherein
each of the fin spacers includes an inner side surface adjacent to the second portion and an outer side surface facing the inner side surface, and
the first source/drain region contacts each of the fin spacers along the outer side surface of each of the fin spacers.
8. The semiconductor device of claim 7 , wherein the first source/drain region contacts the top surface of the field insulating layer.
9. The semiconductor device of claim 1 , further comprising:
a second multi-channel active pattern adjacent to the first multi-channel active pattern and extending along the first direction, the second multi-channel active pattern including,
a third portion having a top surface protruding further in the upward direction than a top surface of the field insulating layer, and
a fourth portion on both sides of the third portion, the fourth portion having a top surface protruding further in the upward direction than the top surface of the field insulating layer and protruding in the upward direction less than the top surface of the third portion; and
a second source/drain region on the fourth portion of the second multi-channel active pattern and contacting the field insulating layer,
wherein the gate electrode is formed on the third portion and the second source/drain region is formed on both sides of the gate electrode.
10. The semiconductor device of claim 9 , wherein the second source/drain region contacts the first source/drain region.
11. The semiconductor device of claim 9 , wherein each of the first source/drain region and the second source/drain region contacts the top surface of the field insulating layer.
12. The semiconductor device of claim 1 , wherein
a height from the top surface of the field insulating layer to the top surface of the first portion is a first height,
a height from the top surface of the field insulating layer to the top surface of the second portion is a second height, and
the first height is greater than the second height.
13. The semiconductor device of claim 1 , wherein an outer circumferential surface of the first source/drain region has at least one of a diamond shape, a circular shape, and a rectangular shape.
14. The semiconductor device of claim 1 , wherein the first multi-channel active pattern is a fin-type active pattern.
15. A semiconductor device comprising:
a multi-channel active pattern defined by a field insulating layer and extending along a first direction, the multi-channel active pattern including,
a first portion having a top surface protruding further in an upward direction than a top surface of the field insulating layer, and
a second portion on both sides of the first portion, the second portion protruding further in the upward direction than the top surface of the field insulating layer and protruding in the upward direction less than the top surface of the first portion;
a gate electrode on the first portion of the multi-channel active pattern, the gate electrode extending along a second direction different from the first direction;
fin spacers on a part of sidewalls of the second portion protruding further in the upward direction than the top surface of the field insulating layer; and
a source/drain region covering at least part of the fin spacers and contacting the top surface and the sidewalls of the second portion protruding further in the upward direction than the fin spacers.
16. The semiconductor device of claim 15 , wherein the source/drain region partially covers the fin spacers.
17. The semiconductor device of claim 16 , wherein
each of the fin spacers comprises an inner side surface adjacent to the second portion protruding further in the upward direction than the top surface of the field insulating layer and an outer side surface facing the inner side surface, and
upper parts of the outer side surfaces of the fin spacers contact the source/drain region and lower parts of the outer side surfaces of the fin spacers do not contact the source/drain region.
18. The semiconductor device of claim 15 , wherein the source/drain region contacts the field insulating layer.
19. A semiconductor device comprising:
a field insulating layer on a substrate;
a first multi-channel active pattern defined by a field insulating layer and extending along a first direction, the multi-channel active pattern including,
a first portion having a top surface protruding further in an upward direction than a top surface of the field insulating layer, and
a second portion on both sides of the first portion, the second portion protruding further in the upward direction than the top surface of the field insulating layer and protruding in the upward direction less than the top surface of the first portion, the second portion having sidewalls with a continuous profile;
a first gate electrode on the first portion of the first multi-channel active pattern, the first gate electrode extending along a second direction different from the first direction;
a first source/drain region surrounding the second portion protruding further in the upward direction than a top surface of the field insulating layer:
a second multi-channel active pattern defined by the field insulating layer and extending along a third direction, the second multi-channel active pattern including,
a third portion having a top surface protruding further in the upward direction than a top surface of the field insulating layer, and
a fourth portion on both sides of the third portion in the third direction, the fourth portion having a top surface protruding further in the upward direction than the top surface of the field insulating layer and protruding in the upward direction less than the top surface of the third portion;
a second gate electrode on the third portion of the second multi-channel active pattern, the second gate electrode extending along a fourth direction different from the third direction;
fin spacers on a part of sidewalls of the fourth portion protruding further in the upward direction than the top surface of the field insulating layer; and
a second source/drain region contacting the top surface and the sidewalls of the fourth portion protruding further than the fin spacers.
20. The semiconductor device of claim 19 , wherein the second source/drain region covers at least a portion of the fin spacers.