Semiconductor memory device and method of controlling the same

1. A storage device comprising:

a nonvolatile semiconductor memory configured to store a plurality of detecting codes to detect an error in a plurality of data items, respectively, a plurality of first correcting codes to correct an error in a plurality of first data blocks, respectively, each of the first data blocks comprising one of the data items and a corresponding detecting code, a second correcting code to correct an error in a second data block which comprises the first data blocks, and the second data block;

a first corrector configured to correct an error in the first data blocks using the first correcting codes, respectively;

a detector configured to detect an error in the data items corrected by the first corrector using the detecting codes, respectively; and

a second corrector configured to correct an error in a data item containing the error of the corrected data items using the second correcting code.

2. The device according to claim 1 , wherein an error correction capability of the second correcting code is higher than error correction capabilities of the first correcting codes.

3. The device according to claim 1 , wherein the second corrector stops a correction process when the data items corrected by the first corrector contain no error.

4. The device according to claim 1 , wherein the detector generates error information representing presence/absence of an error in each of the corrected data items.

5. The device according to claim 1 wherein the semiconductor memory is a NAND flash memory.

6. A storage device comprising:

a nonvolatile semiconductor memory configured to store a plurality of detecting codes to respectively detect an error in a plurality of data items, a plurality of first correcting codes to respectively correct an error in a plurality of first data blocks each of which comprises one of the data items and a corresponding detecting code, a second correcting code to correct an error in a second data block which comprises the first data blocks, and the second data block;

a first corrector receiving the first data blocks and configured to correct an error in the first data blocks using the first correcting codes, respectively;

a detector receiving the data items corrected by the first corrector and configured to detect an error in the corrected data items using the detecting codes, respectively; and

a second corrector receiving the second data block corrected by the first corrector and configured to correct an error in the corrected second data block using the second correcting code, based on a detection result by the detector.

7. The device according to claim 6 , wherein an error correction capability of the second correcting code is higher than error correction capabilities of the first correcting codes.

8. The device according to claim 6 , wherein the second corrector stops a correction process when the data items corrected by the first corrector contain no error.

9. The device according to claim 6 , wherein the detector generates error information representing presence/absence of an error in each of the corrected data items.

10. The device according to claim 6 , wherein the semiconductor memory is a NAND flash memory.

11. A storage device comprising:

a nonvolatile semiconductor memory configured to store first data;

a first corrector configured to correct first error data in the first data using first correcting code data;

a detector configured to detect second error data which has not been corrected by the first corrector, using detecting code data; and

a second corrector configured to correct the second error data using second correcting code data.