Apparatuses and methods for performing compare operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.
1. A method, comprising:
charging an input/output (IO) line of a memory array to a voltage;
activating an access line of the memory array and at least two selected decode lines of the array at the same time; and
determining whether at least one memory cell coupled to the access line stores a compare value by sensing whether the voltage of the IO line changes in response to the activation of the at least two selected decode lines.
2. The method of claim 1 , wherein charging an IO line includes precharging an IO line of the memory array to a precharge voltage.
3. The method of claim 1 , wherein charging the IO line to the voltage includes charging the IO line to a supply voltage.
4. The method of claim 3 , wherein the supply voltage corresponds to a particular data value.
5. The method of claim 1 , wherein charging the IO line to a voltage includes charging the IO line to a ground voltage.
6. The method of claim 5 , wherein the ground voltage corresponds to a particular data value.
7. The method of claim 1 , wherein activating selected decode lines comprises activating a subset of the decode lines of the array.
8. The method of claim 7 , including determining the subset of decode lines based on a set of criteria of the subset.
9. An apparatus comprising:
an array of memory cells;
a controller configured to cause:
precharging of an input/output (IO) line of the array to a precharge voltage;
selective activation of an access line of the array; and
selective activation of at least two decode lines of the array at the same time; and
sensing circuitry coupled to the array and configured to:
sense a number of selected memory cells coupled to the activated access line; and
determine whether the precharge voltage of the IO line changes in response to the activation of the at least two decode lines.
10. The apparatus of claim 9 , wherein the controller comprises an on die controller.
11. The apparatus of claim 9 , wherein the controller comprises an external host.
12. The apparatus of claim 9 , wherein the precharge voltage corresponds to a particular data value and a determined change in the precharge voltage of the IO line indicates that a selected memory cell corresponding to an activated decode line of the decode lines stores a data value other than the particular data value.
13. The apparatus of claim 9 , wherein the sensing circuitry comprises a secondary sense amp configured to detect whether the precharge voltage of the IO line changes.
14. The apparatus of claim 9 , wherein a determined change in the precharge voltage of the IO line indicates data in a memory cell matches a compare value.
15. The apparatus of claim 9 , wherein the control circuitry is configured to report a determined change in the precharge voltage of the IO line to a host.
16. The apparatus of claim 9 , wherein the sensing circuitry is configured to provide an indication that a determined change in the precharge voltage of the IO line was detected.
17. An apparatus comprising:
an array of memory cells;
control circuitry configured to cause:
charging of an input/output (IO) line of the memory array to a voltage;
selective activation of a plurality of access lines at the same time; and
selective activation of at least two decode lines at the same time; and
sensing circuitry coupled to the memory array and configured to determine whether the charged voltage of the IO line changes in response to activation of the at least two decode lines.
18. The apparatus of claim 17 , wherein:
charging an IO line to a voltage includes precharging an IO line of the memory array to a precharge voltage; and
a determined change in the precharge voltage of the IO line indicates that at least one memory cell of memory cells coupled to the access lines matches a compare value.
19. The apparatus of claim 17 , wherein the sensing circuitry comprises a number of accumulators coupled to a respective number of primary sense amplifiers.
20. The apparatus of claim 17 , wherein the sensing circuitry configured to determine whether the charged voltage of the IO line changes comprises a secondary sense amplifier coupled to the IO line.