TESTING OF INTEGRATED CIRCUITS DURING AT-SPEED MODE OF OPERATION
Methods for testing an application specific integrated circuit (ASIC). A set of representations is created that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis. The set of representations are further grouped in the sub-chip into various groups based on overlapping of the set of representations. Then, a set of test control signals is generated corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals. Further, patterns are generated using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.
1 . A computer implemented method for testing an application specific integrated circuit (ASIC), comprising:
creating a set of representations that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis;
grouping the set of representations in the sub-chip into various groups based on overlapping of the set of representations; and
generating a set of test control signals corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals from the set of test control signals.
2 . The method of claim 1 , wherein prior to creating the set of representations:
identifying a critical sub-chip in the ASIC based on power dissipation and IR sensitivity.
3 . The method of claim 2 , wherein identifying a critical sub-chip in the ASIC comprises performing a functional mode analysis, and performing a test mode IR drop analysis including a static IR drop analysis and a dynamic IR drop analysis.
4 . The method of claim 3 , wherein performing a static IR drop analysis comprises identifying a set of hot spots in the sub-chip having a maximum average power hotspot and augmenting a power grid of the set of hot spots having the maximum average power density; and wherein performing a dynamic IR drop analysis comprises using waveforms corresponding to a worst-case at-speed test mode pattern exercising targeted portions of the ASIC.
5 . The method of claim 1 , wherein creating a set of representations corresponding to each clock gate comprises:
identifying eligible clock gates of the set of clock gates;
extracting location and load information for each eligible clock gate of the set of clock gates; and
computing the representation for each eligible clock gate.
6 . The method of claim 1 , wherein grouping the set of representations in each sub-chip into various groups based on overlapping of representations comprises:
extracting a set of overlap graphs from the representations of the eligible clock gates; and
running a coloring scheme on each of the overlap graphs to determine a mapping of a preliminary test control signal of the set of test control signals to the set of clock gates.
7 . The method of claim 6 , wherein running a coloring scheme on each of the overlap graphs comprises:
creating a clock gate connectivity matrix; and
reassigning the color scheme incrementally across the set of overlap graphs.
8 . The method of claim 1 further comprising:
generating patterns using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.
9 . The method of claim 8 , wherein generating patterns comprises:
receiving a set of values of the set of test control signals;
checking for a contention corresponding to the set of values where more than one of the set of values is a logic 1; and
removing a pattern associated with contention dynamically during pattern generation.
10 . The method of claim 1 , wherein generating a set of test control signals such that each clock gate with overlapping representations have different test control signals avoids simultaneous switching of clock gates and resulting IR drop hotspots thereby reducing power consumption during at-speed test mode of operation.
11 . A system for testing an integrated circuit, the system comprising:
a computer system having a test processor, the test processor being coupled to the integrated circuit, the integrated circuit having a set of sub-chips, a plurality of cores and a cache, an I/O port, the test controller being configured to activate a set of clock gates in the set of sub-chips in a neighborhood of the integrated circuit in selective manner during at-speed mode of operation.
12 . The system of claim 11 wherein the test controller, in response to a stimuli from the test processor, is configured to generate a set of test control signals that activates the set of clock gates by:
creating a set of representations that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the integrated circuit for test mode power analysis;
grouping the set of representations in the sub-chip into various groups based on overlapping of the set of representations;
generating a set of test control signals corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals.
13 . A computer implemented method for testing an integrated circuit, comprising:
generating multiple test control signals to activate a set of clock gates in the integrated circuit such that simultaneous switching of the set of clock gates is avoided during at-speed test mode of operation of the integrated circuit.
14 . The method of claim 13 , wherein generating multiple test control signals comprising:
creating a set of representations that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the integrated circuit for test mode power analysis;
grouping the set of representations in the sub-chip into various groups based on overlapping of the set of representations; and
generating multiple test control signals corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals.
15 . A computer implemented method for testing an application specific integrated circuit (ASIC), comprising:
creating a set of representations that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis;
grouping the set of representations in the sub-chip into various groups based on overlapping of the set of representations; and
generating a set of test control signals corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals; and
generating patterns using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.
16 . The method of claim 15 , wherein creating a set of representations corresponding to each clock gate comprises:
identifying eligible clock gates of the set of clock gates;
extracting location and load information for each eligible clock gate of the set of clock gates; and
computing the representation for each eligible clock gate.
17 . The method of claim 15 , wherein grouping the set of representations in each sub-chip into various groups based on overlapping of representations comprises:
extracting a set of overlap graphs from the representations of the eligible clock gates; and
running a coloring scheme on each of the overlap graphs to determine a mapping of a preliminary test control signal of the set of test control signals to the set of clock gates.
18 . The method of claim 15 , wherein running a coloring scheme on each of the overlap graphs comprises:
creating a clock gate connectivity matrix to encapsulate structural path statistics; and
reassigning the color scheme incrementally across the set of overlap graphs to minimize pattern volume overhead and coverage loss.
19 . The method of claim 15 further comprising identifying modifications to a functional enable of the set of clock gates that eliminates simultaneous switching in the sub-chip during the at-speed mode of operation.
20 . The method of claim 15 whereby reducing pattern count during the at-speed mode of operation.