Semiconductor device packages with improved thermal management and related methods
Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. The stack of semiconductor dice may include vias extending through each semiconductor die of the stack for electrically interconnecting the semiconductor dice in the stack to one another and to the substrate. Another semiconductor die may be electrically connected to the stack of semiconductor dice and may be located on a side of the stack of semiconductor dice opposing the substrate. The other semiconductor die may be a heat-generating component configured to generate more heat than each semiconductor die of the stack of semiconductor dice. Electrical connectors may be located laterally adjacent to the vias and may form electrical connections between the substrate and the other semiconductor die in isolation from integrated circuitry of the semiconductor dice in the stack.
1. A method of making a semiconductor device package, comprising:
attaching a stack of semiconductor dice to a substrate, the stack of semiconductor dice comprising vias extending through each semiconductor die of the stack for electrically interconnecting the semiconductor dice in the stack to one another and to the substrate;
positioning another semiconductor die on a side of the stack of semiconductor dice opposing the substrate and electrically connecting the other semiconductor die to the first semiconductor die, the other semiconductor die being a heat-generating component configured to generate more heat than each semiconductor die of the stack of semiconductor dice;
forming a direct electrical connection between the substrate and the other semiconductor die in electrical isolation from integrated circuitry of the semiconductor dice of the stack utilizing electrical connectors located laterally adjacent to the vias;
placing a heat sink on a side of the other semiconductor die opposing the substrate and a thermal interface material between the other semiconductor die and the heat sink; and
placing a passivation material between the other semiconductor die and the thermal interface material.
2. The method of claim 1 , further comprising refraining from thinning the other semiconductor die from a wafer-level thickness as measured in a direction perpendicular to an active surface of the other semiconductor die.
3. The method of claim 1 , wherein forming the direct electrical connection between the substrate and the other semiconductor die utilizing the electrical connectors located laterally adjacent to the vias comprises placing at least one interposer through which the electrical connections extend adjacent to the stack of semiconductor dice between the substrate and the other semiconductor die.
4. The method of claim 1 , wherein placing the thermal interface material between the other semiconductor die and the heat sink comprises placing an electrically conductive thermal interface material between the passivation material and the heat sink.
5. A semiconductor device package, comprising:
a substrate;
a stack of semiconductor dice attached to the substrate, the stack of semiconductor dice comprising vias extending through each semiconductor die of the stack for electrically interconnecting the semiconductor dice in the stack to one another and to the substrate;
another semiconductor die electrically connected to the stack of semiconductor dice and located on a side of the stack of semiconductor dice opposing the substrate, the other semiconductor die being a heat-generating component configured to generate more heat than each semiconductor die of the stack of semiconductor dice;
electrical connectors laterally adjacent to the vias, the electrical connectors forming electrical connections between the substrate and the other semiconductor die in isolation from integrated circuitry of the semiconductor dice in the stack;
a heat sink located on a side of the other semiconductor die opposing the substrate;
a thermal interface material between the other semiconductor die and the heat sink; and
a passivation material located between the other semiconductor die and the thermal interface material.
6. The semiconductor device package of claim 5 , wherein the thermal interface material is electrically conductive.
7. The semiconductor device package of claim 5 , wherein each semiconductor die in the stack between the substrate and the other semiconductor die comprises a memory die and the other semiconductor die comprises a logic die.
8. The semiconductor device package of claim 5 , wherein a thickness of the other semiconductor die as measured in a direction perpendicular to an active surface of the other semiconductor die is about 200 μm or greater.
9. The semiconductor device package of claim 5 , wherein the other semiconductor die is free of vias.
10. The semiconductor device package of claim 5 , wherein the electrical connectors extend through portions of the semiconductor dice in the stack between the substrate and the other semiconductor die.
11. The semiconductor device package of claim 10 , wherein a size and shape of the other semiconductor die is at least substantially equal to a size and shape of each semiconductor die in the stack of semiconductor dice.
12. The semiconductor device package of claim 5 , wherein the substrate and the other semiconductor die are larger in at least one lateral dimension than the semiconductor dice in the stack, and the electrical connectors extend through at least one interposer located adjacent to the stack of semiconductor dice between at least one portion of each of the substrate and the other semiconductor die extending laterally beyond at least one side of the stack of semiconductor dice.
13. The semiconductor device package of claim 12 , wherein the substrate and the other semiconductor die are larger in length and width than a length and width of semiconductor dice in the stack and wherein the at least one interposer peripherally surrounds the stack of semiconductor dice between the substrate and the other semiconductor die between a portion of each of the substrate and the other semiconductor die extending laterally beyond sides of the stack.
14. The semiconductor device package of claim 12 , wherein the at least one interposer is located peripherally adjacent to the stack of semiconductor dice between the substrate and the other semiconductor die and further comprising at least another interposer located peripherally adjacent to the stack of semiconductor dice between the substrate and the other semiconductor die on a side of the stack opposing the at least one interposer, the at least another interposer comprising electrical connectors forming a direct electrical connection between the substrate and the other semiconductor die.