Semiconductor memory device
A semiconductor memory device includes a string of memory cell transistors that are connected to each other in series. A selection transistor is connected between one end of the string of the memory cell transistors and one of a source line and a bit line. A line is selectively connected to a gate electrode of the selection transistor, a driver, or a node that supplies an unselected voltage, or is set to be in a floating state.
1. A semiconductor memory device comprising:
a string of memory cell transistors that are electrically connected in series;
a first selection transistor that is electrically connected between a first end of the string of memory cell transistors and a source line, a gate of the first selection transistor being electrically connected to a first line;
a second selection transistor that is electrically connected between a second end of the string of memory cell transistors and a bit line, a gate of the second selection transistor being electrically connected to a second line;
transfer transistors including a first transistor, a second transistor, a third transistor, and a fourth transistor, the first and second transistors being connected to the first selection transistor, the third and fourth transistors being connected to the second selection transistor, the transfer transistors being controllable to set at least one of the first and second lines to be in a floating state;
a first latch configured to hold information about whether or not a block containing the string of memory cell transistors is a bad block; and
a fifth transistor that is electrically connected to the first latch, a gate of the fifth transistor being electrically connected to a gate of the second transistor and a gate of the fourth transistor.
2. The semiconductor memory device according to claim 1 , further comprising:
an inverter, an input end of the inverter being electrically connected to the gate of the fifth transistor, an output end of the inverter being electrically connected to the gate of the second transistor.
3. The semiconductor memory device according to claim 1 , further comprising:
a first nor gate, an first input end of the first nor gate being electrically connected to the gate of the fifth transistor, an output end of the first nor gate being electrically connected to the gate of the fourth transistor.
4. The semiconductor memory device according to claim 3 , further comprising:
a second nor gate configured to receive a first signal and a second signal, an output end of the second nor gate being electrically connected to a second input end of the first nor gate, the first signal being set to be at a high level when the first signal biases the second line in a bad block.
5. The semiconductor memory device according to claim 1 , further comprising:
a second latch configured to hold information about whether or not the first line is to be set in a floating state.
6. A semiconductor memory device comprising:
a string of memory cell transistors that are electrically connected in series;
a first selection transistor that is electrically connected between a first end of the string of memory cell transistors and a source line, a gate of the first selection transistor being electrically connected to a first line;
a second selection transistor that is electrically connected between a second end of the string of memory cell transistors and a bit line, a gate of the second selection transistor being electrically connected to a second line;
transfer transistors including a first transistor, and a second transistor, the first and second transistors being connected to the first selection transistor, the transfer transistors being controllable to set the first line to be in a floating state;
a first latch configured to hold information about whether or not a block containing the string of memory cell transistors is a bad block; and
a third transistor that is electrically connected to the first latch, a gate of the third transistor being electrically connected to a gate of the second transistor.
7. The semiconductor memory device according to claim 6 , further comprising:
a second latch configured to hold information about whether or not the first line is to be set in a floating state.
8. A semiconductor memory device comprising:
a string of memory cell transistors that are electrically connected in series;
a first selection transistor that is electrically connected between a first end of the string of memory cell transistors and a source line, a gate of the first selection transistor being electrically connected to a first line;
a second selection transistor that is electrically connected between a second end of the string of memory cell transistors and a bit line, a gate of the second selection transistor being electrically connected to a second line;
transfer transistors including a first transistor, and a second transistor, the first and second transistors being connected to the second selection transistor,
the transfer transistors being controllable to set the second line to be in a floating state;
a first latch configured to hold information about whether or not a block containing the string of memory cell transistors is a bad block; and
a third transistor that is electrically connected to the first latch, a gate of the third transistor being electrically connected to a gate of the second transistor.
9. The semiconductor memory device according to claim 8 , further comprising:
a second latch configured to hold information about whether or not the first line is to be set in a floating state.