SRAM bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual input level-shifter
Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. Described is a dual input level-shifter with integrated latch. Described is an apparatus which comprises: a write assist pulse generator operating on a first power supply; one or more pull-up devices coupled to the write assist pulse generator, the one or more pull-up devices operating on a second power supply different from the first power supply; and an output node to provide power supply to a memory cell.
1. A level-shifter comprising:
a first power supply to power a plurality of transistors of the level-shifter;
a first input node to receive a first signal generated by a circuit operating on a second power supply, the second supply being different than the first power supply;
a first n-type transistor to receive the first signal;
a second input node to receive a second signal, which is an inverse of the first signal, the second signal generated by the circuit; and
a second n-type transistor to receive the second signal, the first and second n-type transistors having drain terminals cross-coupled to some of the plurality of transistors.
2. The level-shifter of claim 1 further comprises an output node to generate an output signal according to the first and second signals.
3. The level-shifter of claim 1 , wherein the level-shifter is asynchronous.
4. The level-shifter of claim 1 , wherein the level-shifter is independent of a clock signal.
5. The level-shifter of claim 1 further comprises a third input node coupled to some of the plurality of transistors, the third input node to receive third signal to generate a deterministic output.
6. The level-shifter of claim 5 further comprises an output node to generate an output signal according to the first and second signals or third signal.
7. The level-shifter of claim 1 , wherein some of the plurality of transistors operate as a latch.
8. The level-shifter of claim 1 , wherein the second power supply is higher than the first power supply.
9. The level-shifter of claim 1 , wherein the first power supply is higher than the second power supply.
10. A memory unit comprising:
an array of memory cells;
a column multiplexer coupled to the array of memory cells;
a sense amplifier coupled to the column multiplexer; and
an output data latch with integrated level-shifter includes:
a first power supply to power a plurality of transistors of the level-shifter;
a first input node to receive a first signal generated by a circuit operating on a second power supply, the second supply being different than the first power supply;
a first n-type transistor to receive the first signal;
a second input node to receive a second signal, which is an inverse of the first signal, the second signal generated by the circuit; and
a second n-type transistor to receive the second signal, the first and second n-type transistors having drain terminals cross-coupled to some of the plurality of transistors.
11. The memory unit of claim 10 , wherein the array of memory cells is an array of SRAM cells.
12. The memory unit of claim 10 , further comprises bit line pre-charge coupled to the column multiplexer.
13. The memory unit of claim 10 further comprises an output node to generate an output signal according to the first and second signals.
14. The memory unit of claim 10 , wherein the output data latch with integrated level-shifter is asynchronous.
15. The memory unit of claim 10 , wherein the output data latch with integrated level-shifter is independent of a clock signal.
16. The memory unit of claim 10 further comprises a third input node coupled to some of the plurality of transistors, the third input node to receive third signal to generate a deterministic output.
17. The memory unit of claim 16 further comprises an output node to generate an output signal according to the first and second signals or third signal.
18. The memory unit of claim 10 , wherein some of the plurality of transistors operate as a latch.
19. The memory unit of claim 10 , wherein the second power supply is higher than the first power supply.
20. The memory unit of claim 10 , wherein the first power supply is higher than the second power supply.