IP Library Granted Patent US 9,350,359
Granted Patent B2
US 9,350,359 · App. 14/606,960 · Granted May 24, 2016

Magnetic logic units configured as analog circuit building blocks

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,350,359
App. No.
14/606,960
Granted
May 24, 2016
Kind
B2
Abstract

A circuit includes a magnetic logic unit including input terminals, output terminals, a field line, and magnetic tunnel junctions (MTJs). The field line electrically connects a first and a second input terminal, and is configured to generate a magnetic field based on an input to at least one of the first and the second input terminal. The input is based on an analog input to the circuit. Each MTJ is electrically connected to a first output terminal and a second output terminal, and is configured such that an output of at least one of the first and the second output terminal varies in response to a combined resistance of the MTJs. The resistance of each of the MTJs varies based on the magnetic field. The circuit is configured to generate an analog output based on the output of at least one of the first and the second output terminal.

Claims (43)

1. A circuit, comprising:

a magnetic logic unit including:

a plurality of terminals including a first input terminal, a second input terminal, a first output terminal, and a second output terminal;

a field line that electrically connects the first input terminal and the second input terminal, the field line being configured to generate a magnetic field based on an input to at least one of the first input terminal and the second input terminal, the input being based on an analog input to the circuit; and

a plurality of magnetic tunnel junctions, wherein each of the plurality of magnetic tunnel junctions is electrically connected to the first output terminal and the second output terminal, and is configured such that an output of at least one of the first output terminal and the second output terminal varies in response to a combined resistance of the plurality of magnetic tunnel junctions, wherein the resistance of the each of the plurality of magnetic tunnel junctions varies based on the magnetic field;

wherein the circuit is configured to generate an analog output based on the output of the at least one of the first output terminal and the second output terminal.

2. The circuit of claim 1 , wherein no terminal in the plurality of terminals is in common with any other terminal in the plurality of terminals.

3. The circuit of claim 1 , wherein a bias point of the magnetic logic unit is configured to substantially maximize gain of the magnetic logic unit.

4. The circuit of claim 1 , wherein a bias point of the magnetic logic unit is configured for small signal operation, such that the output varies substantially linearly with the input.

5. The circuit of claim 4 , wherein:

the magnetic logic unit is configured such that the circuit performs amplification of the analog input to generate the analog output; and

the analog output is continuously varying.

6. The circuit of claim 1 , wherein the magnetic logic unit is configured such that the circuit is one of a single stage voltage follower or a single stage current follower.

7. The circuit of claim 1 , wherein the magnetic logic unit is configured such that the circuit is one of an inverting amplifier or a differential amplifier.

8. The circuit of claim 1 , wherein a bias point of the magnetic logic unit is configured for large signal operation, such that the output varies substantially non-linearly with the input.

9. The circuit of claim 8 , wherein:

the magnetic logic unit is configured such that the circuit is configured to be a non-linear analog circuit; and

the analog output is continuously varying.

10. The circuit of claim 1 , wherein the magnetic logic unit is configured such that the circuit is configured to be one of an oscillator or a mixer.

11. The circuit of claim 1 , wherein:

at least one of the plurality of magnetic tunnel junctions includes a storage layer and a sense layer; and

a magnetization direction of the storage layer is pinned during processing by the circuit.

12. The circuit of claim 1 , wherein:

at least one of the plurality of magnetic tunnel junctions includes a storage layer and a sense layer; and

a magnetization direction of the storage layer is pre-configured; and

a direction of current flow through the field line is configurable such that the magnetization direction of the sense layer is switchable based on the current flow through the field line.

13. The circuit of claim 1 , further comprising another magnetic logic unit including:

a plurality of terminals including a first input terminal, a second input terminal, a first output terminal, and a second output terminal;

a field line that electrically connects the first input terminal and the second input terminal, the field line being configured to generate a magnetic field based on an input to at least one of the first input terminal and the second input terminal; and

a plurality of magnetic tunnel junctions, wherein each of the plurality of magnetic tunnel junctions is electrically connected to the first output terminal and the second output terminal, and is configured such that a resistance of the each of the plurality of magnetic tunnel junctions varies based on the magnetic field;

wherein the field line of the magnetic logic unit is biased in a forward direction and the field line of the another magnetic logic is biased in a reverse direction; and

wherein the magnetic logic unit and the another magnetic logic unit are configured such that the circuit is configured to be a differential analog circuit.

14. The circuit of claim 13 , wherein the another magnetic logic unit is configured to be biased by an output current of the magnetic logic unit.

15. The circuit of claim 1 , further comprising another magnetic logic unit, wherein the another magnetic logic unit is configured to be biased by an output current of the magnetic logic unit.

16. The circuit of claim 1 , further comprising another magnetic logic unit, wherein a portion of the circuit including the magnetic logic unit is configured to be a current source that is configured to bias the another magnetic logic unit.

17. The circuit of claim 1 , further comprising another magnetic logic unit, wherein a portion of the circuit including the magnetic logic unit is configured to be an active load of the another magnetic logic unit.

18. The circuit of claim 1 , wherein the field line is serpentine.

19. The apparatus of claim 1 , wherein:

at least one of the plurality of magnetic tunnel junctions includes a storage layer and a sense layer; and

a magnetization direction of the storage layer is pre-configured by at least one of an external field current and an external heating mechanism.

20. The apparatus of claim 1 , wherein:

at least one of the plurality of magnetic tunnel junctions includes a storage layer and a sense layer; and

a magnetization direction of the storage layer is pre-configured by at least one of the field line and an internal heating mechanism.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2024
From: CROCUS TECHNOLOGY SA
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 066350/0669 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2023
From: CROCUS TECHNOLOGY INC.
To: CROCUS TECHNOLOGY SA
Reel/Frame 066157/0629 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT ASSIGNEE NAME IS "CROCUS TECHNOLOGY INC. " AS REFLECTED IN THE COMBINED DECLARATION AND ASSIGNMENT PREVIOUSLY RECORDED AT REEL: 036431 FRAME: 0361. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 23, 2023
From: LEE, DOUGLAS J.; OREN-PINES, YARON; TABATABAEI, SEYED A.; RUMLEY, STUART DESMOND; CAMBOU, BERTRAND F.
To: CROCUS TECHNOLOGY INC.
Reel/Frame 065316/0819 →
RELEASE OF SECURITY INTEREST Recorded Aug 30, 2023
From: LLC "SBERBANK INVESTMENTS"
To: CROCUS TECHNOLOGY, INC.
Reel/Frame 064783/0420 →
SECURITY INTEREST Recorded Apr 13, 2018
From: CROCUS TECHNOLOGY, INC.
To: LLC "SBERBANK INVESTMENTS"
Reel/Frame 045938/0810 →
RELEASE OF SECURITY INTEREST Recorded Apr 9, 2018
From: KREOS CAPITAL IV (LUXEMBOURG) SARL
To: CROCUS TECHNOLOGY, INC.
Reel/Frame 045871/0622 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2015
From: LEE, DOUGLAS J.; OREN-PINES, YARON; TABATABAEI, SEYED A.; RUMLEY, STUART DESMOND; CAMBOU, BERTRAND F.
To: CROCUS TECHNOLOGY INC..
Reel/Frame 036431/0361 →
SECURITY INTEREST Recorded Jun 29, 2015
From: CROCUS TECHNOLOGY, INC.
To: KREOS CAPITAL IV (LUXEMBOURG) SARL
Reel/Frame 036031/0327 →